Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
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May 19, 2025 - C++
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vlsi-design
Here are 253 public repositories matching this topic...
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
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Jul 9, 2023 - Verilog
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
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Jun 18, 2026 - SystemVerilog
微电子和集成电路自学指南
analog circuits verilog circuit vlsi self-learning cmos integrated-circuits circuit-design verilog-a vlsi-design cmos-circuits veriloga
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Jul 23, 2026
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
eda vlsi nthu vlsi-physical-design vlsi-design vlsi-placement vlsi-cad physical-design-automation vlsi-floorplan vlsi-routing two-way-min-cut fixed-outline global-placement global-routing
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Jan 23, 2021 - C++
This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details
digital simulation logic-gates alu vlsi multiplexer cadence-virtuoso andgate orgate 1bitfulladder logicgates vlsi-circuits vlsi-design vlsi-designing vlsi-project 4bitadder 8isto1mux 4bitdivider 4bitmultiplier dflipflop
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Mar 22, 2019
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
rtl verilog fulladder vlsi multiplier hardware-description-language wallace vlsi-design vlsi-project dadda-tree carry-save-adder fast-multiplication dadda-multiplier tree-multipliers
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Jun 6, 2024 - Verilog
A parameterizable Weight-Stationary 2D Systolic Array implemented in Verilog for hardware-accelerated matrix multiplication
google rtl verilog hardware-designs gtkwave vlsi tpu vlsi-design tpu-acceleration chipdesign sillicon systolic-array 2d-systolic-array
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Jul 13, 2026 - Makefile
Microshift Compression: An Efficient Image Compression Algorithm for Hardware
fpga matlab image-processing hardware-architectures verilog image-compression computational-photography image-sensor low-power vlsi-design hdlcoder smart-image-sensor
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Apr 21, 2021 - Verilog
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
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Jan 23, 2024 - Verilog
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
signal-processing fast-fourier-transform digital-signal-processing vlsi-physical-design fpga-accelerator vlsi-design vlsi-project
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May 20, 2020 - Verilog
VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.
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Jul 21, 2025 - C
Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"
machine-learning deep-neural-networks deep-learning neural-network machine-learning-algorithms artificial-intelligence artificial-neural-networks logistic-regression feedforward-neural-network polynomial-regression vlsi machine-intelligence design-automation electronic-design-automation vlsi-circuits vlsi-design vlsi-machine-learning vlsi-deep-learning
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Dec 9, 2018 - Jupyter Notebook
Gatery, a library for circuit design.
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Jul 24, 2026 - Assembly
This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects
protocol verification eda rtl verilog systemverilog alu vlsi modelsim uvm verilog-hdl axi apb ahb verilog-project vlsi-design design-verification vlsi-project axi-lite system-verilog-testbench
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May 23, 2026 - SystemVerilog
ICRTL Benchmark: Industrial-level RTL design challenges for evaluating PPA optimization, code generation, and LLM applications in EDA.
benchmark evolution natural-language ppa eda rtl verilog system-verilog yosys ic-design vlsi-design rtl-design hardware-accelerator ai-agent verilogeval rtllm llm-benchmark spec-to-rtl
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Jul 3, 2026 - SystemVerilog
Contains all the necessary lab tasks (Cadence Virtuoso) for ECE3002 VLSI System Design (VIT).
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Aug 28, 2025
Tutorial, examples and regression tests for Coriolis & Alliance (LIP6)
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Jul 6, 2026 - Python
Spiking Neural Network Accelerator
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May 18, 2022 - SystemVerilog
Learning Path: RISC-V System-on-Chip (SoC) design, from Register Transfer Level (RTL) to a GDSII layout | Complete VLSI design flow using open-source EDA tools.
opensource magic asic rtl icarus-verilog gtkwave yosys risc-v klayout ngspice vlsi-design asic-design openlane gdsii-flow system-on-chip-design
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Nov 25, 2025 - Verilog
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