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pipeline-design

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Low-power fixed-point Softmax processing unit with LUT-based exponentiation and an 8-stage pipelined Mitchell logarithmic divider. Designed in Verilog and implemented on TSMC 180nm using Cadence tools. Achieves 1 output/cycle throughput and 8.9× speedup over sequential division. Patent under review.

  • Updated Apr 2, 2026
opsinist

Run a company of AI agents out of one git repository — any craft, not just code. The team, the process, the history, the cost — all files: clone it and everything travels. Gates that say what enforces them, doors that refuse instead of hoping, evidence on every claim.

  • Updated Aug 9, 2026
  • Shell

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