Master AI inference, AI agent harness systems, and hardware engineering — then design a physical AI chip. That is the goal.
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Updated
May 26, 2026 - HTML
Master AI inference, AI agent harness systems, and hardware engineering — then design a physical AI chip. That is the goal.
AI-powered ESP32 pentesting device with RF replay, RF jammer, IR control and BadUSB capabilities. Built for LilyGO T-Embed CC1101 & LilyGO T-Watch-S3
PMSG is face computer / wearable platform using Seeed Studio XIAO, This where you can find code to flash you device
A Go CLI tool to benchmark local LLMs via Ollama, measuring Time To First Token (TTFT) and throughput on your specific hardware.
🦞 ClawBox — Your private AI assistant on NVIDIA Jetson. Setup wizard, dashboard, and 580+ skills. Plug in, scan QR, done.
AI accelerators, edge inference devices, compilers, runtimes, benchmarks, and research for building and evaluating machine-learning systems.
Garuda: CVXIF coprocessor optimizing batch-1 attention microkernels with 7.5-9× lower p99 latency. RISC-V INT8 MAC accelerator for transformer inference.
Make your own talking skull for halloween in 2 hours.
Provide AI-driven penetration testing with portable hardware tools tailored for cybersecurity research and real-world testing scenarios.
This is the official Arduino library for N2CMU (Neural Network Coprocessing Microcontroller Unit) available on Arduino Package Manager and PlatformIO.
大模型久困云端,故押注百年未来于“AI硬件+端云协同”,期待着AGI与真实幻境的完美重叠。也是祈光的原意之一:祈光同行。 We Are Praying for Light.
Feedforward Neural Network Coprocessing Microcontroller Unit (CPC via UART) for STM32F103C8T6 Bluepill Development Board written purely in TinyGo.
SystemVerilog implementations of fundamental neural network structures, designed for synthesis on FPGAs.
T1C — Open-Source AI Accelerator Architecture. Like RISC-V did for CPUs, T1C does for AI chips. Fully open source, MIT Licensed.
End-to-end ASIC SoC design and functional verification of a lightweight machine learning accelerator using SystemVerilog and UVM. Includes Python automation for test generation and result analysis. Built to simulate real-world ML silicon validation at scale.
Open-source data, checklists, and frameworks behind breezehw.com — BOM pricing at 1K volume, DFM rules, NRE budgets, and FCC/CE/UKCA/RCM/CCC certification navigation for AI hardware founders.
Open hardware desktop AI node: 4× Tesla V100, 128GB HBM2, PCIe/NVLink topology and V-Core liquid/air cooling.
Rivos — RISC-V AI silicon for data center
The biggest computing revolution is coming. Quantum supremacy, brain-computer 10 Gbit/s thoughts, DNA as storage, light replacing electrons, chips that think like brains, and ambient intelligence everywhere. Computing 2040 — the future of thought & power.
Hardware-level AI Matrix Multiplication Accelerator (Systolic Array) in SystemVerilog using AXI4-Stream, verified via Python & Cocotb co-simulation.
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