Digital-Assignment-02

Sainet Chaubey

Name		Name	Last commit message	Last commit date
Latest commit History 26 Commits
Qu.1_Sec.2_New_fifo_systemVerilog		Qu.1_Sec.2_New_fifo_systemVerilog
README.md		README.md
Screenshot 2026-01-31 015130.png		Screenshot 2026-01-31 015130.png
Screenshot 2026-02-02 225752.png		Screenshot 2026-02-02 225752.png
Screenshot 2026-02-02 233103.png		Screenshot 2026-02-02 233103.png
Screenshot 2026-02-03 022305.png		Screenshot 2026-02-03 022305.png
Screenshot 2026-02-03 022329.png		Screenshot 2026-02-03 022329.png
Screenshot 2026-02-03 153637.png		Screenshot 2026-02-03 153637.png
Screenshot 2026-02-03 154205.png		Screenshot 2026-02-03 154205.png
Screenshot 2026-02-03 162215.png		Screenshot 2026-02-03 162215.png
Screenshot 2026-02-04 010103.png		Screenshot 2026-02-04 010103.png
Screenshot 2026-02-05 231805.png		Screenshot 2026-02-05 231805.png
Screenshot 2026-02-05 232253.png		Screenshot 2026-02-05 232253.png
clk_gating_controller		clk_gating_controller
full_adder_sv_with_test_bench		full_adder_sv_with_test_bench
master_and_slave		master_and_slave
master_slave_handshake		master_slave_handshake
new_file.py		new_file.py
seq_div_5_sv		seq_div_5_sv
sv_design_logic_question		sv_design_logic_question
sv_gate_controller		sv_gate_controller
test_bench_clk_gating_controller		test_bench_clk_gating_controller

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