Skip to content

Pull requests: riscv/sail-riscv

New pull request New
100 Open 1,014 Closed
100 Open 1,014 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Assigned to nobody Loading
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

Add the Svade and Svadu extensions. extension Adds support for a RISC-V extension
#1599 opened Mar 7, 2026 by pmundkur Loading…
6
Refactor feature_enabled_for_priv() to return tri-state result
#1597 opened Mar 6, 2026 by nadime15 Loading…
2
Add the Svnapot extension. extension Adds support for a RISC-V extension
#1596 opened Mar 6, 2026 by pmundkur Loading…
5
Add a missed check for invalid PTE. will be merged Scheduled to be merged soon if nobody objects
#1595 opened Mar 5, 2026 by pmundkur Loading…
7
add unratified RISC-V Zbr0p93 ext
#1593 opened Mar 5, 2026 by KotorinMinami Loading…
2
Use a wrapper to ensure that xtval_exception_value is used for constructed traps. will be merged Scheduled to be merged soon if nobody objects
#1592 opened Mar 5, 2026 by pmundkur Loading…
11
Make the physical memory write helpers require an explicit access-type argument. will be merged Scheduled to be merged soon if nobody objects
#1590 opened Mar 4, 2026 by pmundkur Loading…
2
Add a partial implementation of Sdtrig.
#1588 opened Mar 3, 2026 by pmundkur • Draft
2
Support more general symbolic excution in isla
#1585 opened Mar 3, 2026 by msuadOf Loading…
Add unratified Zvfbfa extension (Draft)
#1581 opened Mar 2, 2026 by TinyuengKwan • Draft
5
add configuration option for reserved behavior vsew >= 100.
#1573 opened Feb 28, 2026 by challenger1024 Loading…
4
Add a max_steps_to_wait parameter to configure maximum waits for waiting instructions. configuration Additional configuration settings needed for the model
#1568 opened Feb 27, 2026 by pmundkur Loading…
1
17
Add failure reasons for CSR accesses for debugging logs
#1562 opened Feb 24, 2026 by pmundkur • Draft
4
Refactor CSR access checking to handle virtual-instruction exceptions. refactor Code clean up
#1556 opened Feb 20, 2026 by pmundkur Loading…
1
16
Make medeleg.Fetch_Addr_Align read-only zero when Ext_Zca is enabled.
#1550 opened Feb 13, 2026 by KotorinMinami Loading…
8
Add first party memory model with support for memory dumps
#1549 opened Feb 13, 2026 by Timmmm • Draft
1
1
rename memory.misaligned.allowed_within_exp
#1548 opened Feb 13, 2026 by KotorinMinami Loading…
3
Add Hypervisor Instructions
#1545 opened Feb 12, 2026 by nadime15 • Draft
2
Lean emulator
#1541 opened Feb 10, 2026 by Ptival Loading…
19
Legalize xret privilege with respect to misa.
#1539 opened Feb 7, 2026 by pmundkur Loading…
1
7
Add per field mutable_misa config options
#1524 opened Feb 4, 2026 by jordancarlin Loading…
1
5
Add Hypervisor 2-Stage Address Translation
#1513 opened Jan 30, 2026 by nadime15 • Draft
36
Simplify translationException refactor Code clean up
#1502 opened Jan 26, 2026 by trdthg Loading…
5
[Zvdot4a8i] Adding description of Zvdot4a8i's vdot4a* instruction (BUILD but UNTESTED) extension Adds support for a RISC-V extension
#1495 opened Jan 19, 2026 by nibrunieAtSi5 • Draft
16
Add the Zicclsm extension. extension Adds support for a RISC-V extension tgmm-agenda Tagged for the next Golden Model meeting agenda.
#1468 opened Jan 6, 2026 by challenger1024 Loading…
68
ProTip! Follow long discussions with comments:>50.