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Pull requests: llvm/circt

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Pull requests list

[RTG] Randomizer operations are not pure RTG Involving the `rtg` dialect
#10560 opened May 29, 2026 by maerhart Member Loading…
3
[ESI][Runtime] Windows support for esiaccel.pytest extensions ESI
#10559 opened May 29, 2026 by teqdruid Contributor Loading…
7
[Moore][ImportVerilog] Replace $sformat/$swrite string dispatch with ksn
#10557 opened May 28, 2026 by VecoMr Contributor Loading…
1
[Moore][Sim][SV] Add $strobe[boh] lowering via sim.defer
#10556 opened May 28, 2026 by VecoMr Contributor • Draft
2
[OM] Simplify evaluator placeholder handling, NFCI
#10555 opened May 28, 2026 by uenoku Member Loading…
1
[RFC][Sim] Add declarations and reads for externally controlled configuration bits
#10552 opened May 27, 2026 by nanjo712 Contributor Loading…
5
[FIRRTLToHW] Support printing SimulationTime in lower-to-core
#10551 opened May 27, 2026 by nanjo712 Contributor Loading…
1
[Arc] Lower hw.triggered in Arc
#10550 opened May 27, 2026 by nanjo712 Contributor Loading…
1
[ImportVerilog] Add support for countones.
#10549 opened May 27, 2026 by jpienaar Member Loading…
1
[FIRRTLToHW] Add support for lower-to-core in firrtl.fflush
#10545 opened May 26, 2026 by nanjo712 Contributor Loading…
14
[LTL] Add ClockedAtomOp description
#10541 opened May 24, 2026 by Clo91eaf Contributor Loading…
5
[FIRRTLToHW] Remove the SYNTHESIS guard in printf/flush lowering path
#10526 opened May 22, 2026 by nanjo712 Contributor Loading…
17
[Arc] Add coroutine ops Arc Involving the `arc` dialect
#10522 opened May 21, 2026 by fabianschuiki Contributor Loading…
5
[FIRRTL] EliminateWires: preserve sv.attributes when converting WireOp to NodeOp
#10519 opened May 21, 2026 by bheneffe Loading…
14
[Synth] Add SAT-based exact synthesis pass
#10493 opened May 18, 2026 by uenoku Member Loading…
1
Bump slang 11.0
#10488 opened May 16, 2026 by mi-and-core • Draft
1
[ImportVerilog] Preserve declaration order across regular and interface-modport ports
#10468 opened May 14, 2026 by micprog Contributor Loading…
18
[HW] Add forceable wire support with HW RefType
#10447 opened May 12, 2026 by prithayan Contributor • Draft
[DRAFT][FIRRTLToHW] Emit sim.proc.print instead of sim.print
#10441 opened May 12, 2026 by nanjo712 Contributor • Draft
Add results to sv.ifdef
#10436 opened May 12, 2026 by prithayan Contributor • Draft
2
[Sim] Extract common logic of ProceduralizeSim for reuse
#10422 opened May 9, 2026 by nanjo712 Contributor Loading…
6
[FIRRTL] Add mux2cell/mux4cell canonicalization patterns
#10414 opened May 8, 2026 by anaumchev Loading…
2
1
[debug][firrtl] Carry Chisel source-level types through the pipeline
#10410 opened May 7, 2026 by fkhaidari Loading…
3
[HW] HWVectorization Part 4: Partial Vectorization (Chunking)
#10399 opened May 6, 2026 by mafeguimaraes Contributor Loading…
[Support] Add parallel instance graph visitors
#10353 opened Apr 29, 2026 by seldridge Member • Draft
4
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