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edwarddavidbakeredwarddavidbaker
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Merge pull request #362 from edwarddavidbaker/sync-platforms
SRF, GRR, PTL, LNL, ARL, MTL, ADL: Release event updates
2 parents 88f4921 + 996baca commit 3bcb5f6

27 files changed

+733
-263
lines changed

‎ADL/events/alderlake_goldencove_core.json‎

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{
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"Header": {
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"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
4-
"Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.36",
5-
"DatePublished": "11/17/2025",
6-
"Version": "1.36",
3+
"Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
4+
"Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.37",
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"DatePublished": "01/13/2026",
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"Version": "1.37",
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"Legend": ""
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},
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"Events": [

‎ADL/events/alderlake_gracemont_core.json‎

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{
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"Header": {
3-
"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
4-
"Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.36",
5-
"DatePublished": "11/17/2025",
6-
"Version": "1.36",
3+
"Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
4+
"Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.37",
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"DatePublished": "01/13/2026",
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"Version": "1.37",
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"Legend": ""
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},
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"Events": [
1010
{
1111
"EventCode": "0x00",
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"UMask": "0x01",
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"EventName": "INST_RETIRED.ANY",
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"BriefDescription": "Counts the total number of instructions retired. (Fixed event)",
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"BriefDescription": "Fixed Counter: Counts the total number of instructions retired.",
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"PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0.",
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"Counter": "Fixed counter 0",
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"PEBScounters": "32",
@@ -36,7 +36,7 @@
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"EventCode": "0x00",
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"UMask": "0x02",
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"EventName": "CPU_CLK_UNHALTED.CORE",
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"BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)",
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"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
4040
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
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"Counter": "Fixed counter 1",
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"PEBScounters": "33",
@@ -86,7 +86,7 @@
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"EventCode": "0x00",
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"UMask": "0x03",
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"EventName": "CPU_CLK_UNHALTED.REF_TSC",
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"BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)",
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"BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles at TSC frequency.",
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"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
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"Counter": "Fixed counter 2",
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"PEBScounters": "34",
@@ -836,7 +836,7 @@
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"EventCode": "0x3c",
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"UMask": "0x00",
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"EventName": "CPU_CLK_UNHALTED.CORE_P",
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"BriefDescription": "Counts the number of unhalted core clock cycles.",
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"BriefDescription": "Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD_P]",
840840
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.",
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"Counter": "0,1,2,3,4,5",
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"PEBScounters": "0,1,2,3,4,5",

‎ADL/events/alderlake_uncore.json‎

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{
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"Header": {
3-
"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
4-
"Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.36",
5-
"DatePublished": "11/17/2025",
6-
"Version": "1.36",
3+
"Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
4+
"Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.37",
5+
"DatePublished": "01/13/2026",
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"Version": "1.37",
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"Legend": ""
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},
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"Events": [

‎ADL/events/alderlake_uncore_experimental.json‎

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{
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"Header": {
3-
"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
4-
"Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.36",
5-
"DatePublished": "11/17/2025",
6-
"Version": "1.36",
3+
"Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
4+
"Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.37",
5+
"DatePublished": "01/13/2026",
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"Version": "1.37",
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"Legend": ""
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},
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"Events": [

‎ARL/events/arrowlake_crestmont_core.json‎

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{
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"Header": {
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"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
4-
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.15",
5-
"DatePublished": "11/20/2025",
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"Version": "1.15",
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"Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
4+
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.16",
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"DatePublished": "01/13/2026",
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"Version": "1.16",
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"Legend": ""
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},
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"Events": [
@@ -12,8 +12,8 @@
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"UMask": "0x01",
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"UMaskExt": "0x00",
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"EventName": "INST_RETIRED.ANY",
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"BriefDescription": "Fixed Counter: Counts the number of instructions retired",
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"PublicDescription": "Fixed Counter: Counts the number of instructions retired",
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"BriefDescription": "Fixed Counter: Counts the number of instructions retired.",
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"PublicDescription": "Fixed Counter: Counts the number of instructions retired.",
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"Counter": "Fixed counter 0",
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"PEBScounters": "32",
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"SampleAfterValue": "2000003",
@@ -39,8 +39,8 @@
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"UMask": "0x02",
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"UMaskExt": "0x00",
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"EventName": "CPU_CLK_UNHALTED.CORE",
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"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
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"PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
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"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
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"PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
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"Counter": "Fixed counter 1",
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"PEBScounters": "33",
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"SampleAfterValue": "2000003",
@@ -93,8 +93,8 @@
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"UMask": "0x03",
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"UMaskExt": "0x00",
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"EventName": "CPU_CLK_UNHALTED.REF_TSC",
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"BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
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"PublicDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
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"BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles.",
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"PublicDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles.",
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"Counter": "Fixed counter 2",
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"PEBScounters": "34",
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"SampleAfterValue": "2000003",

‎ARL/events/arrowlake_lioncove_core.json‎

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{
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"Header": {
3-
"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
4-
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.15",
5-
"DatePublished": "11/20/2025",
6-
"Version": "1.15",
3+
"Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
4+
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.16",
5+
"DatePublished": "01/13/2026",
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"Version": "1.16",
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"Legend": ""
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},
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"Events": [

‎ARL/events/arrowlake_skymont_core.json‎

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{
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"Header": {
3-
"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
4-
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.15",
5-
"DatePublished": "11/20/2025",
6-
"Version": "1.15",
3+
"Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
4+
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.16",
5+
"DatePublished": "01/13/2026",
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"Version": "1.16",
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"Legend": ""
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},
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"Events": [
@@ -39,8 +39,8 @@
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"UMask": "0x02",
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"UMaskExt": "0x00",
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"EventName": "CPU_CLK_UNHALTED.CORE",
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"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.",
43-
"PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.",
42+
"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
43+
"PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
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"Counter": "Fixed counter 1",
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"PEBScounters": "33",
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"SampleAfterValue": "2000003",

‎ARL/events/arrowlake_uncore.json‎

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{
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"Header": {
3-
"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
4-
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.15",
5-
"DatePublished": "11/20/2025",
6-
"Version": "1.15",
3+
"Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
4+
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.16",
5+
"DatePublished": "01/13/2026",
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"Version": "1.16",
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"Legend": ""
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},
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"Events": [

‎ARL/events/arrowlake_uncore_experimental.json‎

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{
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"Header": {
3-
"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
4-
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.15",
5-
"DatePublished": "11/20/2025",
6-
"Version": "1.15",
3+
"Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
4+
"Info": "Performance Monitoring Events for Intel(R) Core(TM) processors based on Arrow Lake performance hybrid architecture - V1.16",
5+
"DatePublished": "01/13/2026",
6+
"Version": "1.16",
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"Legend": ""
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},
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"Events": [

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