[TritonGEN] Use GenISA for 2D block store 32b_4r4x1c#6535
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whitneywhtsang merged 1 commit intomainfrom Apr 1, 2026
Merged
[TritonGEN] Use GenISA for 2D block store 32b_4r4x1c#6535whitneywhtsang merged 1 commit intomainfrom
whitneywhtsang merged 1 commit intomainfrom
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Signed-off-by: Whitney Tsang <whitney.tsang@intel.com>
chengjunlu
approved these changes
Apr 1, 2026
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Fixes #6529
CI: https://github.com/intel/intel-xpu-backend-for-triton/actions/runs/23820551218