Skip to content

Add saturating add/sub intrinsics to RISC-V vector backend #9185

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
rajeshgangam wants to merge 1 commit into
base: main
Choose a base branch
from
+8 −0
Open

Add saturating add/sub intrinsics to RISC-V vector backend #9185

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 4 additions & 0 deletions src/CodeGen_RISCV.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -62,6 +62,8 @@ struct RISCVIntrinsic {
const RISCVIntrinsic signed_intrinsic_defs[] = {
{"vaadd", Type::Int, "halving_add", {Type::Int, Type::Int}, AddVLArg | RoundDown | Commutes},
{"vaadd", Type::Int, "rounding_halving_add", {Type::Int, Type::Int}, AddVLArg | RoundUp | Commutes},
{"vsadd", Type::Int, "saturating_add", {Type::Int, Type::Int}, AddVLArg | Commutes},
{"vssub", Type::Int, "saturating_sub", {Type::Int, Type::Int}, AddVLArg},
{"vwadd", {Type::Int, 2}, "widening_add", {Type::Int, Type::Int}, AddVLArg | MangleReturnType | Commutes},
{"vwsub", {Type::Int, 2}, "widening_sub", {Type::Int, Type::Int}, AddVLArg | MangleReturnType},
{"vwmul", {Type::Int, 2}, "widening_mul", {Type::Int, Type::Int}, AddVLArg | MangleReturnType | Commutes},
Expand All @@ -70,6 +72,8 @@ const RISCVIntrinsic signed_intrinsic_defs[] = {
const RISCVIntrinsic unsigned_intrinsic_defs[] = {
{"vaaddu", {Type::UInt}, "halving_add", {Type::UInt, Type::UInt}, AddVLArg | RoundDown | Commutes},
{"vaaddu", {Type::UInt}, "rounding_halving_add", {Type::UInt, Type::UInt}, AddVLArg | RoundUp | Commutes},
{"vsaddu", {Type::UInt}, "saturating_add", {Type::UInt, Type::UInt}, AddVLArg | Commutes},
{"vssubu", {Type::UInt}, "saturating_sub", {Type::UInt, Type::UInt}, AddVLArg},
{"vwaddu", {Type::UInt, 2}, "widening_add", {Type::UInt, Type::UInt}, AddVLArg | MangleReturnType | Commutes},
{"vwsubu", {Type::UInt, 2}, "widening_sub", {Type::UInt, Type::UInt}, AddVLArg | MangleReturnType},
{"vwmulu", {Type::UInt, 2}, "widening_mul", {Type::UInt, Type::UInt}, AddVLArg | MangleReturnType | Commutes},
Expand Down
4 changes: 4 additions & 0 deletions test/correctness/simd_op_check_riscv.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -96,6 +96,10 @@ class SimdOpCheckRISCV : public SimdOpCheckTest {
check("vaaddu.vv", lanes, halving_add(u_1, u_2));
check("vaadd.vv", lanes, rounding_halving_add(i_1, i_2));
check("vaaddu.vv", lanes, rounding_halving_add(u_1, u_2));
check("vsadd.vv", lanes, saturating_add(i_1, i_2));
check("vsaddu.vv", lanes, saturating_add(u_1, u_2));
check("vssub.vv", lanes, saturating_sub(i_1, i_2));
check("vssubu.vv", lanes, saturating_sub(u_1, u_2));

// Widening intrinsics
if (base_bit_width < 64) {
Expand Down