FPGA-Powered Solar Photovoltaic Module Defect Classification

Note: This repository contains the code and implementation details for the paper "FPGA-Powered Solar Photovoltaic Module Defect Classification: Patch-Wise Reusable CNN IPs for High-Speed Edge Processing", accepted in the Journal of Computing and Information Science in Engineering (JCISE).

Overview

This project presents a lightweight MobileNet-based Convolutional Neural Network (CNN) architecture designed for low-latency defect classification in solar photovoltaic (PV) modules. The system is deployed on a Xilinx ZYNQ ZCU104 FPGA board, leveraging High-Level Synthesis (HLS) to create optimized hardware accelerators.

The core contribution involves four reusable Intellectual Property (IP) cores designed for:

1. Standard Convolution
2. Depthwise Convolution
3. Pointwise Convolution
4. Batch Normalization

These engines enable efficient, patch-wise inference on embedded devices, achieving high accuracy with minimal computational cost.

Key Features

• Reusable CNN IPs: Modular hardware engines designed to handle various layer dimensions through zero-padding and surrogate input carriers.
• High Performance:
  • Pointwise IP: 0.07 ms execution time
  • Convolution IP: 0.02 ms execution time
  • Depthwise IP: 0.13 ms execution time
  • Batch Normalization: 0.07 ms execution time
• Accuracy:
  • 91% (2-Class Classification)
  • 86% (8-Class Classification)
  • 79% (11-Class Classification)
  • 86% (12-Class Classification)
• Optimized Implementation: Utilizes loop unrolling, pipelining, and array partitioning for maximum parallelism on the FPGA.

Directory Structure

• HLS Implementation/: Contains the C++ source code for the HLS IP cores.
  • mobilenet.cpp: The main source file defining the MobileNet layers and operations.
  • mobilenet_tb.cpp: Testbench for verifying the design.
• Optimized IPs/: Contains specific optimized IP implementations for different layer types (abtbn, abtconv, abtpw, unidw).

Prerequisites

To reproduce the results or synthesize the IPs, you will need:

• Hardware: Xilinx ZYNQ ZCU104 Evaluation Board.
• Software:
  • Xilinx Vitis HLS 2022.1 (for IP synthesis)
  • Xilinx Vivado 2022.1 (for bitstream generation)
  • Python 3.x (for training and board interaction)

Implementation & Usage

1. Software Design (Training)

The model was trained using TensorFlow/Keras on the InfraredSolarModules dataset. Weights and biases were extracted and saved as text/header files for the HLS implementation.

2. Hardware Design (HLS)

The C++ code in HLS Implementation/ is used to synthesize the hardware IPs.

Important

Configuration Required: The provided source code (mobilenet.cpp and mobilenet_tb.cpp) contains hardcoded absolute paths to weight and bias text files (e.g., C:\Users\VICTUS\Desktop\New Model\...).

Before running synthesis or simulation:

1. Locate the weight/bias files (not currently in this repo root, you may need to generate them or update the paths if you have them locally).
2. Update the #include directives in mobilenet.cpp to match the actual location of these files on your system.

Example of paths to update:

#include "C:\Users\VICTUS\Desktop\New Model\conv1_b.txt"
#include "C:\Users\VICTUS\Desktop\New Model\conv1_w.txt"
// ... and others throughout the file

3. Hardware Implementation

• Export the synthesized IPs as RTL.
• Create a block design in Vivado integrating the Zynq Processing System (PS) with the four custom IPs via AXI Interconnect.
• Generate the bitstream (.bit) and hardware handoff (.hwh) files.
• Deploy to the ZCU104 board using PYNQ or a similar overlay loader.

Architecture & Results

System Architecture

The architecture uses a hardware-software co-design approach where the ARM-based Processing System (PS) manages data transfer via AXI-Lite, and the Programmable Logic (PL) executes the heavy convolution operations.

Performance on ZCU104

IP Core	Computation Time (ms)	Throughput (GOps)
Convolution	0.02	239.2 (Fixed)
Depthwise	0.13	14.7 (Fixed)
Pointwise	0.07	53.7 (Fixed)
Batch Norm	0.07	9.5 (Fixed)

Citation

If you use this code or work, please cite the paper:

G. Vinod, R. M. R. Yanamala, R. D. A. Raj, et al., "FPGA-Powered Solar Photovoltaic Module Defect Classification: Patch-Wise Reusable CNN IPs for High-Speed Edge Processing," Journal of Computing and Information Science in Engineering, 2025. doi:10.1115/1.4070331