fix(ulp): correct LP I2C interrupt wait cycle duration (IDFGH-17203)

[puyogo-suzuki]

Description

This pull request updates the lp_core_i2c module to improve how I2C interrupt wait timeouts are handled. The main change is switching from a software-based loop counter to using the RISC-V mcycle CSR for more accurate and robust cycle counting.

• Replaced the manual increment of a timeout counter with reading the RISC-V mcycle CSR to measure elapsed cycles for timeouts in lp_core_i2c_wait_for_interrupt, improving accuracy and reliability.
• Added #include "riscv/csr.h" to access CSR functions.

Related

None.

Testing

This is a test case repository: https://github.com/puyogo-suzuki/esp-lpi2c-timeout
I tested on ESP32-C6 with the latest ESP-IDF (master branch).

I connected Pin 6 (LPI2C SDA) to GND.
The expected behavior is that lp_core_i2c_master_read_from_device returns ESP_ERR_TIMEOUT after cycles_to_wait cycles.

#define LP_I2C_TRANS_TIMEOUT_CYCLES 5000

uint8_t data_rd[2];
uint32_t start = RV_READ_CSR(mcycle);
lp_core_i2c_master_read_from_device(LP_I2C_NUM_0, 16, data_rd, sizeof(data_rd), LP_I2C_TRANS_TIMEOUT_CYCLES);
uint32_t end = RV_READ_CSR(mcycle);
uint32_t result = end - start;

I measured the elapsed cycles by reading mcycle.
However, before this PR, the result was approximately 30x longer than LP_I2C_TRANS_TIMEOUT_CYCLES (= 150000).

This PR improves the precision of the timeout.
result will be reduced to approx. 5300, which is closer to LP_I2C_TRANS_TIMEOUT_CYCLES.

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[meetpatelvgec]

Hi @puyogo-suzuki
Thanks a lot for submitting this change to improve I2C performance in ULP. We will be reviewing your changes internally and get back to you soon.

[sudeep-mohanty]

sha=ea27268c7e613fce27210d810790af001afa6168

[safocl]

Will these changes work on non-RISCV based chips?

[puyogo-suzuki]

This change only affects RISC-V based chips, as the codebase for Xtensa based chips is different.
The i2c_wait_for_interrupt function for such chips is defined here:

esp-idf/components/ulp/ulp_riscv/ulp_core/ulp_riscv_i2c.c

Lines 70 to 75 in 97d9585

	static inline int32_t ulp_riscv_i2c_wait_for_interrupt(int32_t cycles_to_wait)
	{
	uint32_t status = 0;
	uint32_t to = 0;
	while (1) {

Because the read_from_device and write_to_device functions for non-RISC-V based chips do not take the wait_to_cycles argument, I've left them as is for now.
I can create a separate PR for those if requested.

[meetpatelvgec]

Hi @safocl, @puyogo-suzuki
I have merged my code changes into master branch 7b30754. The changes are slightly more structured and cover SPI, I2C and UART instead of only I2C. They cover both ULP RISC-V and ULP LP Core chips. As far as ESP32 is concerned, it only has ULP FSM, so I think full I2C master/slave functionality won't work on the low power core of ESP32.

[puyogo-suzuki]

Thanks 👍

[safocl]

Hi @safocl, @puyogo-suzuki I have merged my code changes into master branch 7b30754. The changes are slightly more structured and cover SPI, I2C and UART instead of only I2C. They cover both ULP RISC-V and ULP LP Core chips. As far as ESP32 is concerned, it only has ULP FSM, so I think full I2C master/slave functionality won't work on the low power core of ESP32.

I meant that it is generally present in the general file #include "riscv/csr.h", although it is clearly only for risc-v. (in components/ulp/lp_core/lp_core/include/ulp_lp_core_utils.h)