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Signed-off-by: gatecat <gatecat@ds0.me>
Signed-off-by: gatecat <gatecat@ds0.me>
Signed-off-by: gatecat <gatecat@ds0.me>
Signed-off-by: gatecat <gatecat@ds0.me>
Signed-off-by: gatecat <gatecat@ds0.me>
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Requires chipsalliance/python-fpga-interchange#112 and YosysHQ/nextpnr#767
Unfortunately I'm running into a hard-to-debug Vivado segfault when running timing analysis, so I've had to disable that for now (as a workaround running timing analysis manually on the DCP in the GUI works fine).