[VeeR] Add Support for DCLS configuration parameters

[moidx]

This issue is to request the integration of VeeR's Dual Core Lock Step (DCLS) configuration in a future release of the Caliptra Core design.

Design Opens

• Determine if DCLS should be provided as configuration parameter at the top level or if should be mandated for all Caliptra integrations.
• Close on micro-architecture/design opens
  • [DCLS] Evaluate physical hardening of corruption error and disable corruption detection signals. Cores-VeeR-EL2#407
  • [DCLS] Support Target Core Selection in Trace Dump Cores-VeeR-EL2#408
  • Currently a fatal alert is generated by ORing all the bits in the CALIPTRA_ERROR_FATAL register. There needs to be some additional logic to decode the multi-bit DCLS error signal. Account for multi-bit encoding in masking infrastructure managed by the ROM.
    • Review ROM implementation to determine if we want to have masking available to mask
      DCLS errors.
  • Review error detection flows to make sure the DCLS multibit encoding is taken into account.
  • Integrate trace buffer into Caliptra SS MCI. If DCLS is enabled we should send both traces to MCI. The MCI buffer depth can be left as-is.

Define integration plan for Caliptra Core

• Run all top level test cases with DCLS enabled.
• Implement a top level test to dump traces from the selected core. Pending resolution of the design open above.
• Test DCLS control and reporting signals. This will serve as an SoC reference integration test.
• Inject a fault on one of the cores to see the fault logic trigger an error (negative test case).
• Need to quality/check the AXI control signals. Any faults detected by one of the cores should result in a DCLS mismatch alert.
• VeeR test plan review.

Security assessment.

• Document security claims of the design and implementation guidelines.
• Consider publishing a security assessment report to accompany the integration specification.

Feature request for Caliptra SS: chipsalliance/caliptra-ss#476

[kgugala]

#737 adds DCLS core integration into calitpra-rtl. DCLS feature can be enabled with the RV_LOCKSTEP_ENABLE compile time parameter. Both trace interfaces are routed out of the caliptra-rtl module. DCLS runtime signals are routed to the top level of the caliptra-rtl module.

chipsalliance/caliptra-ss#634 adds integration into caliptra-ss. It adds additional CSRs controlling runtime DCLS signals (error injection and dcls disable). The PR also adds trace muxing and CSRs controlling the mux. Trace data is stored in the MCI trace buffer.

The RTL implementation of the feature and integration is done. We're working on the tests