Fix write_verilog escape seq Issue 3826

network/VerilogNamespace.cc

@@ -77,6 +77,7 @@ portVerilogName(const char *sta_name)
   return staToVerilog2(sta_name);
 }
 
+// Unescaping logic should follow reverse of verilogToSta logic
 static string
 staToVerilog(const char *sta_name)
 {
@@ -88,15 +89,14 @@ staToVerilog(const char *sta_name)
   for (const char *s = sta_name; *s ; s++) {
     char ch = s[0];
     if (ch == verilog_escape) {
+      escaped = true;
       char next_ch = s[1];
       if (next_ch == verilog_escape) {
-	escaped_name += ch;
+        // Only keep the character after "\"
+        // to remove the escape added by verilogToSta"
 	escaped_name += next_ch;
 	s++;
       }
-      else
-	// Skip escape.
-	escaped = true;
     }
     else {
       if ((!(isalnum(ch) || ch == '_')))
@@ -113,6 +113,8 @@ staToVerilog(const char *sta_name)
     return string(sta_name);
 }
 
+// Unescaping logic should follow reverse of verilogToSta logic
+// For "\\" handling, this should be like staToVerilog
 static string
 staToVerilog2(const char *sta_name)
 {
@@ -126,15 +128,12 @@ staToVerilog2(const char *sta_name)
   for (const char *s = sta_name; *s ; s++) {
     char ch = s[0];
     if (ch == verilog_escape) {
+      escaped = true;
       char next_ch = s[1];
       if (next_ch == verilog_escape) {
-	escaped_name += ch;
 	escaped_name += next_ch;
 	s++;
       }
-      else
-	// Skip escape.
-	escaped = true;
     }
     else {
       bool is_brkt = (ch == bus_brkt_left || ch == bus_brkt_right);

test/regression_vars.tcl

@@ -166,6 +166,7 @@ record_public_tests {
   report_json1
   report_json2
   suppress_msg
+  test_write_verilog_escape
   verilog_attribute
   verilog_specify
 }

test/test_write_verilog_escape.ok

@@ -0,0 +1,18 @@
+module multi_sink (clk);
+ input clk;
+
+ wire \alu_adder_result_ex[0] ;
+
+ hier_block \h1\x  (.childclk(clk),
+    .\Y[2:1] ({\alu_adder_result_ex[0] ,
+    \alu_adder_result_ex[0] }));
+endmodule
+module hier_block (childclk,
+    \Y[2:1] );
+ input childclk;
+ output [1:0] \Y[2:1] ;
+
+
+ BUFx2_ASAP7_75t_R \abuf_$100  (.A(childclk));
+ BUFx2_ASAP7_75t_R \ff0/name  (.A(childclk));
+endmodule

test/test_write_verilog_escape.tcl

@@ -0,0 +1,14 @@
+# Check if "h1\x" and \Y[2:1] are correctly processed from input to output of Verilog
+read_liberty gf180mcu_sram.lib.gz
+read_liberty asap7_small.lib.gz
+read_verilog test_write_verilog_escape.v
+link_design multi_sink
+write_verilog test_write_verilog_escape_out.v
+set input_file "test_write_verilog_escape_out.v"
+set fp [open $input_file r]
+while {[gets $fp line] >= 0} {
+    puts $line
+}
+close $fp
+file delete "test_write_verilog_escape_out.v"
+

test/test_write_verilog_escape.v

@@ -0,0 +1,15 @@
+
+module \multi_sink (clk);
+ input clk;
+ wire \alu_adder_result_ex[0] ;
+ \hier_block \h1\x (.childclk(clk),  .\Y[2:1] ({ \alu_adder_result_ex[0] , \alu_adder_result_ex[0]  }) );
+endmodule // multi_sink
+
+module \hier_block (childclk, \Y[2:1] );
+   input childclk; 
+   output [1:0] \Y[2:1] ;
+   wire [1:0] \Y[2:1] ;
+   BUFx2_ASAP7_75t_R \abuf_$100  (.A(childclk));
+   BUFx2_ASAP7_75t_R \ff0/name (.A(childclk));
+endmodule // hier_block1
+

verilog/VerilogWriter.cc

@@ -388,7 +388,8 @@ VerilogWriter::writeInstBusPin(const Instance *inst,
   if (!first_port)
     fprintf(stream_, ",\n    ");
 
-  fprintf(stream_, ".%s({", network_->name(port));
+  string port_vname = portVerilogName(network_->name(port)); 
+  fprintf(stream_, ".%s({", port_vname.c_str());
   first_port = false;
   bool first_member = true;