Physical Design Engineer · RTL → GDSII · Samsung 4nm & TSMC 5nm
Building a chip-design toolchain in my spare time — core, SoC, SDK, and a parametric SRAM compiler.
Senior Physical Design at DreamBig Semiconductor (recently acquired by Arm for our RDMA & Chiplet Hub work). I close advanced-node SoCs on Samsung 4nm, focused on power-grid architecture, flow automation, and timing convergence. Highlights:
- 🧩 Designed a self-aligning multilayer PG mesh — modular "Lego-block" grids that snap together across subblocks with consistent VDD/VSS rail alignment.
- 🔬 Wrote a recursive TCL via-stack analyzer and via-ladder methodology for high-current buffers and clock drivers.
- 🧠 Built a connected-components / flood-fill TSV detection algorithm that auto-shifts NoC buffer paths around clustered TSV regions; extended to backside metal for HBM JEDEC bus routing.
- 📡 Authored an internal-patent methodology for buffering & shielding ARM CMN interconnects (~2 GHz, 2000+ signals).
A connected ecosystem around NTiny — the first truly indigenously-designed microprocessor taped out in Pakistan (NUST × TSMC 65nm, where I was on the core design team) — and the open EDA tooling around it.
| Project | What it is | Stack |
|---|---|---|
| 🔥 ntiny | The taped-out RISC-V SoC — runs Linux. RV32IMCB, 4-stage in-order pipeline, M/S/U privilege with Sv32 MMU, JTAG + RISC-V Debug, full peripheral set (UART/SPI/I²C/PWM/Timers/PLIC/GPIO/CRC). Silicon validated on a custom PCB. | SystemVerilog · TSMC 65nm |
| 🧠 ntiny-ooo | A classical Tomasulo out-of-order successor: per-FU reservation stations, ROB, 3-wide CDB, per-branch RAT snapshots for single-cycle mispredict recovery. RV32IM + Zicsr + Zb* + Zicond. RISCOF + directed test battery (11/11 green). | SystemVerilog · Verilator · spike |
| 📦 ntiny-sdk | Software SDK for the NTiny SoC, shipped as an Open-CMSIS-Pack — works in Keil, IAR, STM32CubeIDE, Eclipse, and VS Code. SVD, drivers, FreeRTOS, CoreMark, Dhrystone, and 10+ example apps. | C · CMSIS · GCC · FreeRTOS |
| 🧮 PakFPU | IEEE-754 compliant floating-point unit for the open-source community. Parameterizable FP32/FP64 with FMA, division, and square root. Verified against Berkeley TestFloat across all 5 rounding modes; IEEE corner cases (sNaN, ±Inf×±0, canonical qNaN, FDIV ready/valid handshake) proven with SymbiYosys + Bitwuzla formal. Ships with the ntiny SoC. | SystemVerilog · Verilator · SymbiYosys |
| 🧱 fabram | A parametric SRAM compiler targeting sky130A. Give it (words, bits, mux) → get a hierarchical SPICE netlist, a Liberty .lib from ngspice characterization (3×3 LUTs, setup/hold bisection), and a Verilog model with a specify block. Includes a Bayesian cell-sizing optimizer. |
Python · ngspice · sky130A |
| ⚙️ spice_gen | A PDK-aware SPICE netlist generator from YAML topology descriptions. Multi-dialect (ngspice / hspice / spice3), hierarchical deps:, automatic M→X conversion for subcircuit PDKs. Backbone of fabram. |
Python · Pydantic |
How they fit together: spice_gen emits the netlists. fabram uses it to compose SRAM blocks from cell YAMLs, characterizes them with ngspice, and writes Liberty + Verilog. ntiny is the taped-out core (with PakFPU as its FPU); ntiny-ooo is its OoO successor; ntiny-sdk is how software runs on either.
RISCV ⭐19 — 32-bit soft RV32IMF processor for FPGAs (DE10-Lite, Avalon bus, GPIO/UART/Timer). CoreMark 2.58/MHz, Dhrystone 1.45 DMIPS/MHz. The ancestor of ntiny. AES-256-Verilog · SM4-Verilog — Synthesizable block ciphers. RISCV-Compliant-Divider · RV32_with_MAC — RV32 extensions. OpenCV-Maze-Solving · Water-Management-System — Older CV / embedded projects.
Physical Design Synopsys Fusion Compiler · Custom Compiler · ICV · PrimeTime
Cadence Innovus · Genus · Virtuoso · PVS · RedHawk
RTL & Verification SystemVerilog · DPI-C · Verilator · VCS · QuestaSim
RISCOF · Berkeley TestFloat · SymbiYosys · Bitwuzla
Analog & SPICE ngspice · hspice · sky130A · Liberty characterization
Scripting Python · TCL · C/C++ · Bash · Makefile
Domains Advanced-node PD · PG mesh · RDL · 3DIC / Chiplet · HBM3 · ARM CMN
RISC-V (in-order & OoO) · CMSIS · FreeRTOS
MS, Electrical Engineering (ICs & Systems) — NUST · GPA 4.00/4.00 · 2024
Thesis: A commercially-compatible memory compiler framework for automated SRAM array generation — productized as fabram.
BS, Electrical Engineering — NUST · 2021
FYP: Event-based image processing for drone obstacle avoidance.
Always happy to chat about advanced-node PD, RISC-V microarchitecture, parametric memory generation, or chiplet integration.