Reed-Solomon-Generator

Generate Reed-Solomon encoder/decoder hardware (Verilog) from high-level specifications.

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Table of Contents

1. Project Overview
2. Prerequisites
3. Installation & Setup
4. Quick Start
5. Generating Verilog
6. Running the Test Suite
7. Project Structure
8. Contributing
9. License & Acknowledgements

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Project Overview

The Reed-Solomon-Generator repository provides a Python-based toolchain that:

• Takes Reed-Solomon parameters (field size, irreducible polynomial, parity length, etc.) and produces synthesizable Verilog modules.
• Supports three main hardware blocks:

Block	Source file	Description
RS Segment Generator	src/generators/RSSegmentVerilog.py	Generates the per-segment multiplier logic used by the accumulator.
RS Accumulator	src/generators/RSAccumulatorVerilog.py	Implements the core Reed-Solomon accumulator (parity calculation).
RS AXI-Stream ECC Generator	src/generators/RSAXISVerilog.py	Wraps the accumulator with an AXI-Stream front-end for easy integration in FPGA designs.

The generated Verilog can be dropped into an any RTL project and connected to other IP blocks via the provided AXI-Stream interface.

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Prerequisites

This project is developed in Devcontainer Docker environment other ways are probably possible but not supported. Defined in Dockerfile and in PyProject.toml

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Installation & Setup

1. Clone the repository

   git clone git@github.com:SatLab-AGH/Reed-Solomon-ECC-Generator.git
   cd reed-solomon-generator

2. Open the devcontainer

   If you use VSCode with Remote-Containers, the configuration lives in .devcontainer/devcontainer.json. Opening the folder in VSCode will automatically spin up a Docker container with all extensions listed (Python, C/C++, Verilog, Ruff, etc.).

3. Sync Python environment with uv

   uv sync --active  # installs dependencies from pyproject.toml

4. (For contributors) Install pre-commit

   pre-commit install

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Quick Start

Below is a minimal example command that generates a complete Verilog module for a Reed-Solomon encoder with 10-bit symbols and 16 parity symbols.

/workspace/.venv/bin/python /workspace/src/main.py --WORD_SIZE 10 --ECC_LEN 16 --OUTPUT_DIR output 

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Generating Verilog

The core generation flow is:

1. Mastrovito matrix MastrovitoMatrix creates the multiplication matrix needed for GF(2^m) operations.
2. Segment multiplier RSSegmentVerilog uses the matrix and the list of constant multiplicants to emit per-segment Verilog.
3. Accumulator RSAccumulatorVerilog wires the segment modules together and adds the parity-generation logic.
4. AXI-Stream wrapper RSAXISVerilog adds the AXI-Stream interface and feedback control.

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Running the Test Suite

The repository ships with a pytest-compatible test suite under tests/.

. ./scripts/mcore_regr.sh

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Contributing

1. Fork the repository and create a feature branch.

2. Run the pre-commit hooks before committing:

   pre-commit run --all-files

3. Write tests for any new functionality.

4. Submit a Merge Request via GitHub.

Note: Main work is done on SatLab AGH internal repository, any features and bugs will be worked on there and then merged to main mirrored to GitHub for the time project is developed for SatLab AGH.

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License & Acknowledgements

This repository is shared via MIT License.

This code is developed for DZIDA Laser Communication Project for a PUCHACZ Sattelite mission.

Jan Rosa is developer contributing to Reed-Solomon Encoder Module.

Mateusz Maź is developer contributing to Reed-Solomon Decoder Module.

Huge thanks people contributing to:

• reedsolo
• cocotb
• cocotbext-axi
• verilator
• Icarus Verilog

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