1.0.1

Update

• A bug of CoRAM signal insertion for nested instance/module is fixed (tests/multipage)
• Minor typos are fixed.

Test environment

Mac OSX 10.10.5

• python 2.7.9 + pyverilog 1.0.1
• python 3.4.2 + pyverilog 1.0.1

Ubuntu 14.04

• python 2.7.6 + pyverilog 1.0.1
• python 3.4.3 + pyverilog 1.0.1

1.0.0

The stable release of PyCoRAM.

Update

• sys.path settings is chanegd.
• examples and tests are separated.
• library scripts and executable scripts are separated.
• setup.py is updated for module dependency.

Test environment

Mac OSX 10.10.5

• python 2.7.9 + pyverilog 1.0.1
• python 3.4.2 + pyverilog 1.0.1

Ubuntu 14.04

• python 2.7.6 + pyverilog 1.0.1
• python 3.4.3 + pyverilog 1.0.1

0.9.3

Avalon support is improved.

0.9.2

(1) timeout is supported in iochannel.
(2) FIFO status can be read by using a read operation to 0x0004 in iochannel.
(3) iochannel_read/write task in test bench are updated to use polling.

0.9.1

New sample programs are added. Some bugs are fixed.

0.9.0

PyCoRAM 0.9.0 supports both AMBA AXI4 bus and Altera Avalon bus.

Not only master interface (as known as AXI4 master and Avalon master), but also slave interface (as known as AXI4 slave and Avalon slave) is supported. The software executed on a soft-processor (such as Microblaze) can easily accesses in general memory-mapped device manner using volatile variable.
In order to support both Python 3.4 and Python 2.7, AST visiting patterns of Control-thread HLS is modified.

Some new examples on actual FPGAs are added: shortest path search (dijkstra), matrix multiplication, stencil computation, etc.

0.8.0-public

PyCoRAM 0.8.0 is released.

This version includes 2 example accelerator project using PyCoRAM.

• Matrix-matrix Multiplication
• 9-point stencil computation

This version uses Pyverilog 0.7.0 for code parsing and dataflow analysis.

0.7.0-public

PyCoRAM 0.7.0-public with Pyverilog 0.6.0-lite.