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Experiment: Try different technology parameters for RAM/ROM config files

Status: Open.

#13 In NYU-Processor-Design/nyu-mem;

· SPD3 opened on Apr 27, 2023

Module: Generate ROM script

Status: Open.

#12 In NYU-Processor-Design/nyu-mem;

· SPD3 opened on Apr 27, 2023

Module: Hex to Verilog translator

In Progress

Status: Open.

#4 In NYU-Processor-Design/nyu-mem;

· SPD3 opened on Mar 6, 2023

Module: ROM/RAM parameterized decoder

Status: Open.

#3 In NYU-Processor-Design/nyu-mem;

· SPD3 opened on Mar 6, 2023

Module: Memory Control Unit

needs to be outlined

Status: Open.

#2 In NYU-Processor-Design/nyu-mem;

· SPD3 opened on Mar 6, 2023