Welcome to my collection of SystemC-based lab projects, implemented as part of the Hardware/Software Co-Design and System-Level Digital Design course at K. N. Toosi University of Technology.
Each project demonstrates a fundamental or advanced digital concept modeled using SystemC, from simple logic gates to full FSM-based systems with interrupt controllers and waveform tracing.
| Lab | Title | Key Concepts |
|---|---|---|
| 01 | XOR Gate in SystemC | Basic logic gate modeling |
| 02 | 8-bit ALU | Arithmetic & logical operations |
| 03 | Instruction Memory Loader | ROM simulation, file input |
| 04 | RAM (TBD) | Read/Write memory |
| 05 | FSM-Controlled Counter with MUX | FSM, Counter, MUX, waveform trace |
| 06 | Single Interrupt System | Peripheral interrupt simulation |
| 07 | Multi-Interrupt System with Priority | Multi-interrupt arbitration |
⚠️ Note: All source files are written in SystemC, tested using Visual Studio, and many include.vcdwaveform files for timing analysis using tools like GTKWave.
SystemC-Lab-Projects/
├── Lab01_XOR/
├── Lab02_ALU/
├── Lab03_InstructionMemory/
├── Lab04_RAM/
├── Lab05_FSM_Counter_MUX/
├── Lab06_SingleInterrupt/
├── Lab07_MultiInterrupt/
└── README.md ← You are hereEach lab folder contains:
- ✅ Well-commented C++ SystemC source code
- 📄 Individual
README.mdwith description and output - 📈 Optional waveform files (
.vcd) - 🖼️ Image files (diagrams, waveform screenshots)
These projects were developed under the supervision of faculty in the System-Level Design Lab and are aimed at enhancing practical experience in:
- ⏱️ Timed Hardware Simulation
- 💻 Hardware/Software Integration
- 🧮 Instruction & Memory Modeling
- 🔁 FSM-based Architecture Design
- 🔔 Interrupt Systems
AliAkbar Mohsennejad
B.Sc. Student in Electrical Engineering – Digital Systems
K. N. Toosi University of Technology
🔗 LinkedIn |
systemc digital-design fsm interrupts memory alu waveform simulation hardware kntu