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docs: fixed some grammar mistakes
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docs/pages/inspiration.md

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- micro-architecture (comparing the single-cycle, multi-cycle and the pipeline processor)
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- microinstructions
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and so much more, which I don't want to go into detail here as it goes way beyond the scope of this project. Overall, it was an awesome lecture, in which I was able to gain much new knowledge in that area. In the end, I had a good understanding of how these computers operate and what the different micro-steps are to execute a single instruction.
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But were much more topics, which I don't want to go into detail here as it goes way beyond the scope of this project. Overall, it was an awesome lecture, in which I was able to gain much new knowledge in that area. In the end, I had a good understanding of how these computers operate and what the different micro-steps are to execute a single instruction.
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With the new gained knowledge, I started my research what it takes to build an 8-Bit breadboard computer like the one from Ben Eater. I re-watched some of the old videos, searched the [Ben Eater subreddit](https://www.reddit.com/r/beneater/) for tips and tricks during building and found people improving upon Ben's design. In the end, I settled onto two key points:
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docs/pages/instruction-set/details.md

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:point_right: Click to switch representation:
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[Instruction Set Overview](./overview){: .btn .btn-outline}
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[OpCode Matrix](./opcode-matrix){: .btn .btn-outline}
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[Opcode Matrix](./opcode-matrix){: .btn .btn-outline}
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[Instruction Details](./details){: .btn .btn-green}
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docs/pages/instruction-set/opcode-matrix.md

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:point_right: Click to switch representation:
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[Instruction Set Overview](./overview){: .btn .btn-outline}
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[OpCode Matrix](./opcode-matrix){: .btn .btn-green}
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[Opcode Matrix](./opcode-matrix){: .btn .btn-green}
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[Instruction Details](./details){: .btn .btn-outline}
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docs/pages/instruction-set/overview.md

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:point_right: Click to switch representation:
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[Instruction Set Overview](./overview){: .btn .btn-green}
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[OpCode Matrix](./opcode-matrix){: .btn .btn-outline}
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[Opcode Matrix](./opcode-matrix){: .btn .btn-outline}
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[Instruction Details](./details){: .btn .btn-outline}
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docs/pages/modules/7-segment-display.md

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One of these features is the multiplexing of the display's digits: The EEPROM has only eight I/O pins, meaning that no more than one digit can be controlled at once. In order to represent all possible numbers (-128 to 127), we need a minimum number of four digits on the display (one for the negative sign and three for any three-digit number).
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The solution for displaying four digits simultaneously is multiplexing:
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<br>
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Only one of the four digits is active at the same time, but the module cycles through the digits so quickly, that the human eye recognizes it as if all digits were shown at the same time. In order to decode which of the 4 digits is active at the moment, the decoder/EEPROM needs an additional two bits. The last address bit available is used for switching the lookup-table between the normal decimal representation and a hexadecimal one.
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Only one of the four digits is active at the same time, but the module cycles through the digits so quickly, that the human eye recognizes it as if all digits were shown at the same time. In order to decode which of the 4 digits is active at the moment, the decoder/EEPROM needs an additional two bits. The last address-bit available is used for switching the lookup-table between the normal decimal representation and a hexadecimal one.
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Three chips of the module's schematic have not been described in the upper section yet.
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The first one is a 555 timer chip, which controls the speed of the multiplexing, meaning how quickly it cycles through the digits.

docs/pages/modules/b-c-registers.md

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They use two 4-bit register chips (SN74LS173AN) and a single 8-bit bus transceiver (SN74LS245N) each, which controls outputting data to the bus. <br>
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Technically, the 4-bit register chips even have a three-state output, so an extra 8-bit bus transceiver wouldn't be necessary. But always enabling the output of the registers and controlling the output to the bus with the bus transceiver allows me to hook up LED's to the registers outputs and thus displaying their contents permanently, not only when outputting to the bus. <br>
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Asynchronous resets provides the ability to reset the registers to zero, the CLK-input provides a synchronization for loading data from the bus (on the rising CLK edge). On the other hand, outputting data from the register to the bus is asynchronous, as the bus transceiver outputs data immediately after it's Output Enable signal goes low.
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Asynchronous resets provide the ability to reset the registers to zero, the CLK-input provides a synchronization for loading data from the bus (on the rising CLK edge). On the other hand, outputting data from the register to the bus is asynchronous, as the bus transceiver outputs data immediately after it's Output Enable signal goes low.
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<br>
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### B-Register

docs/pages/modules/controller.md

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The computer supports the four most common flags coming from the ALU: Zero, Negative, Carry and Overflow.
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So the naive approach is to use four of the controller EEPROMs address pins/inputs in order to input all flag (combination) to the controller.
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Unfortunately, there was only one address line left on these EEPROMs (12/13 are already used for the 4-bit step counter and the 8-bit opcode), so i had to came up with a solution to that problem.
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Unfortunately, there was only one address line left on these EEPROMs (12/13 are already used for the 4-bit step counter and the 8-bit opcode), so I had to come up with a solution to that problem.
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<br>
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In fact, every instruction uses at most one (combination) of the flags above, so I'm able to introduce a multiplexer and some combinatorial logic to route always only one flag to the controller.
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The three upper bits of the opcodes are fed into the control lines of that multiplexer, which means that theres a [range of opcodes]({{ site.baseurl }}/instruction-set/opcode-matrix#table2) where a specific flag (combination) is available.
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The three upper bits of the opcodes are fed into the control lines of that multiplexer, which means that there's a [range of opcodes]({{ site.baseurl }}/instruction-set/opcode-matrix#table2) where a specific flag (combination) is available.
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If you define an instruction, you must ensure that, if the instruction needs a specific flag, its opcode lies within the range where that needed flag is available.
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### Control Line Decoders
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That enables me to introduce two 4-to-16 bit decoders to the circuit, one for most of the input enable (IE) control lines and one for the output enable (OE) control lines.
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The control bits of the decoders are connected to four outputs of the control EEPROMs each, but in return, I get 16 new control lines per EEPROM, resulting in a total of 3\*8+2\*16 = 56 control lines that I have available to control all of my modules.
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### Annoying behaviour of the 28C64B
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### Annoying behavior of the 28C64B
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The 28C64B EEPROMs have an annoying behaviour: When their address/input lines change, their outputs are undefined for a short period of time, until the correct value for the next input is loaded and the outputs stabilize again.
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The 28C64B EEPROMs have an annoying behavior: When their address/input lines change, their outputs are undefined for a short period of time, until the correct value for the next input is loaded, and the outputs stabilize again.
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For some control lines, that's not an issue, because they are only read on the rising edge of the clock signal (like most input enable (IE) lines for example).
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But for some others, this results in a misbehaviour of the module and thus the entire computer. The issue is that during this undefined time period, there may be a spike on a control line.
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On the other hand, some modules are very sensitive to such spikes. As an example, have a look at the INC_X control line: As soon as there is a short spike on that line, the register increments. But if that spike occurs unintentionally, the register may increment without you specifying this in your assembly code.
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But for some others, this results in a misbehavior of the module and thus the entire computer. The issue is that during this undefined time period, there may be a spike on a control line.
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On the other hand, some modules are very sensitive to such spikes. As an example, take a look at the INC_X control line: As soon as there is a short spike on that line, the register increments. But if that spike occurs unintentionally, the register may increment without you specifying this in your assembly code.
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That's why you must avoid these spikes on some control lines at all cost.
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<br>
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The solution is a simple circuit called a ["low pass filter"](https://en.wikipedia.org/wiki/Low-pass_filter), consisting of just a single resistor and a capacitor.

docs/pages/modules/reset.md

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## Reset
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The reset module basically consists of a single button and a not gate which allows to send an active low or an active high reset signal to all other modules after the button was pressed (which you should do after every power-up, or when you just want to rerun your program).
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The reset module basically consists of a single button and a not gate which allows sending an active low or an active high reset signal to all other modules after the button was pressed (which you should do after every power-up, or when you just want to rerun your program).
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### Why do we even need a reset signal at all?
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