-
Notifications
You must be signed in to change notification settings - Fork 0
Expand file tree
/
Copy pathhex_7seg.v
More file actions
77 lines (71 loc) · 1.92 KB
/
hex_7seg.v
File metadata and controls
77 lines (71 loc) · 1.92 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
module hex_7seg(
input [3:0] cs,
input [3:0] ds,
input [3:0] s,
input [3:0] das,
output reg [6:0] seg0,
output reg [6:0] seg1,
output reg [6:0] seg2,
output reg [6:0] seg3
);
always @(cs[3:0]) begin
case (cs[3:0])
4'b0000: seg0 <= 7'b1_00_00_00;
4'b0001: seg0 <= 7'b1_11_10_01;
4'b0010: seg0 <= 7'b0_10_01_00;
4'b0011: seg0 <= 7'b0_11_00_00;
4'b0100: seg0 <= 7'b0_01_10_01;
4'b0101: seg0 <= 7'b0_01_00_10;
4'b0110: seg0 <= 7'b0_00_00_10;
4'b0111: seg0 <= 7'b1_11_10_00;
4'b1000: seg0 <= 7'b0_00_00_00;
4'b1001: seg0 <= 7'b0_01_00_00;
default: seg0 <= 7'b1_11_11_11;
endcase
end
always @(ds[3:0]) begin
case (ds[3:0])
4'b0000: seg1 <= 7'b1_00_00_00;
4'b0001: seg1 <= 7'b1_11_10_01;
4'b0010: seg1 <= 7'b0_10_01_00;
4'b0011: seg1 <= 7'b0_11_00_00;
4'b0100: seg1 <= 7'b0_01_10_01;
4'b0101: seg1 <= 7'b0_01_00_10;
4'b0110: seg1 <= 7'b0_00_00_10;
4'b0111: seg1 <= 7'b1_11_10_00;
4'b1000: seg1 <= 7'b0_00_00_00;
4'b1001: seg1 <= 7'b0_01_00_00;
default: seg1 <= 7'b1_11_11_11;
endcase
end
always @(s[3:0]) begin
case (s[3:0])
4'b0000: seg2 <= 7'b1_00_00_00;
4'b0001: seg2 <= 7'b1_11_10_01;
4'b0010: seg2 <= 7'b0_10_01_00;
4'b0011: seg2 <= 7'b0_11_00_00;
4'b0100: seg2 <= 7'b0_01_10_01;
4'b0101: seg2 <= 7'b0_01_00_10;
4'b0110: seg2 <= 7'b0_00_00_10;
4'b0111: seg2 <= 7'b1_11_10_00;
4'b1000: seg2 <= 7'b0_00_00_00;
4'b1001: seg2 <= 7'b0_01_00_00;
default: seg2 <= 7'b1_11_11_11;
endcase
end
always @(das[3:0]) begin
case (das[3:0])
4'b0000: seg3 <= 7'b1_00_00_00;
4'b0001: seg3 <= 7'b1_11_10_01;
4'b0010: seg3 <= 7'b0_10_01_00;
4'b0011: seg3 <= 7'b0_11_00_00;
4'b0100: seg3 <= 7'b0_01_10_01;
4'b0101: seg3 <= 7'b0_01_00_10;
4'b0110: seg3 <= 7'b0_00_00_10;
4'b0111: seg3 <= 7'b1_11_10_00;
4'b1000: seg3 <= 7'b0_00_00_00;
4'b1001: seg3 <= 7'b0_01_00_00;
default: seg3 <= 7'b1_11_11_11;
endcase
end
endmodule