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mr-cmr-c
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x86 avx512 loadu: almost all of the remaining intrinsics
1 parent a860f4f commit 69f0da1

2 files changed

Lines changed: 1908 additions & 1 deletion

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‎simde/x86/avx512/loadu.h‎

Lines changed: 328 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,10 @@
2828
#define SIMDE_X86_AVX512_LOADU_H
2929

3030
#include "types.h"
31+
#include "mov.h"
32+
#include "../avx.h"
33+
#include "../sse2.h"
34+
#include "../sse.h"
3135

3236
HEDLEY_DIAGNOSTIC_PUSH
3337
SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
@@ -141,9 +145,191 @@ simde_mm512_loadu_si512 (void const * mem_addr) {
141145
#define simde_x_mm512_loadu_epu32(mem_addr) simde_mm512_loadu_si512(mem_addr)
142146
#define simde_x_mm512_loadu_epu64(mem_addr) simde_mm512_loadu_si512(mem_addr)
143147

148+
SIMDE_FUNCTION_ATTRIBUTES
149+
simde__m128i
150+
simde_mm_mask_loadu_epi8(simde__m128i src, simde__mmask16 k, void const * mem_addr) {
151+
#if defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE)
152+
return _mm_mask_loadu_epi8(src, k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
153+
#else
154+
return simde_mm_mask_mov_epi8(src, k, simde_mm_loadu_epi16(mem_addr));
155+
#endif
156+
}
157+
#if defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
158+
#undef _mm_mask_loadu_epi8
159+
#define _mm_mask_loadu_epi8(src, k, mem_addr) simde_mm_mask_loadu_epi8(src, k, mem_addr)
160+
#endif
161+
162+
SIMDE_FUNCTION_ATTRIBUTES
163+
simde__m128i
164+
simde_mm_maskz_loadu_epi8(simde__mmask16 k, void const * mem_addr) {
165+
#if defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE)
166+
return _mm_maskz_loadu_epi8(k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
167+
#else
168+
return simde_mm_maskz_mov_epi8(k, simde_mm_loadu_epi8(mem_addr));
169+
#endif
170+
}
171+
#if defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
172+
#undef _mm_maskz_loadu_epi8
173+
#define _mm_maskz_loadu_epi8(k, mem_addr) simde_mm_maskz_loadu_epi8(k, mem_addr)
174+
#endif
175+
176+
SIMDE_FUNCTION_ATTRIBUTES
177+
simde__m128i
178+
simde_mm_mask_loadu_epi16(simde__m128i src, simde__mmask8 k, void const * mem_addr) {
179+
#if defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE)
180+
return _mm_mask_loadu_epi16(src, k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
181+
#else
182+
return simde_mm_mask_mov_epi16(src, k, simde_mm_loadu_epi16(mem_addr));
183+
#endif
184+
}
185+
#if defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
186+
#undef _mm_mask_loadu_epi16
187+
#define _mm_mask_loadu_epi16(src, k, mem_addr) simde_mm_mask_loadu_epi16(src, k, mem_addr)
188+
#endif
189+
190+
SIMDE_FUNCTION_ATTRIBUTES
191+
simde__m128i
192+
simde_mm_maskz_loadu_epi16(simde__mmask8 k, void const * mem_addr) {
193+
#if defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE)
194+
return _mm_maskz_loadu_epi16(k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
195+
#else
196+
return simde_mm_maskz_mov_epi16(k, simde_mm_loadu_epi16(mem_addr));
197+
#endif
198+
}
199+
#if defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
200+
#undef _mm_maskz_loadu_epi16
201+
#define _mm_maskz_loadu_epi16(k, mem_addr) simde_mm_maskz_loadu_epi16(k, mem_addr)
202+
#endif
203+
204+
SIMDE_FUNCTION_ATTRIBUTES
205+
simde__m128i
206+
simde_mm_mask_loadu_epi32(simde__m128i src, simde__mmask8 k, void const * mem_addr) {
207+
#if defined(SIMDE_X86_AVX512F_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE)
208+
return _mm_mask_loadu_epi32(src, k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
209+
#else
210+
return simde_mm_mask_mov_epi32(src, k, simde_mm_loadu_epi32(mem_addr));
211+
#endif
212+
}
213+
#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
214+
#undef _mm_mask_loadu_epi32
215+
#define _mm_mask_loadu_epi32(src, k, mem_addr) simde_mm_mask_loadu_epi32(src, k, mem_addr)
216+
#endif
217+
218+
SIMDE_FUNCTION_ATTRIBUTES
219+
simde__m128i
220+
simde_mm_maskz_loadu_epi32(simde__mmask8 k, void const * mem_addr) {
221+
#if defined(SIMDE_X86_AVX512F_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE)
222+
return _mm_maskz_loadu_epi32(k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
223+
#else
224+
return simde_mm_maskz_mov_epi32(k, simde_mm_loadu_epi32(mem_addr));
225+
#endif
226+
}
227+
#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
228+
#undef _mm_maskz_loadu_epi32
229+
#define _mm_maskz_loadu_epi32(k, mem_addr) simde_mm_maskz_loadu_epi32(k, mem_addr)
230+
#endif
231+
232+
SIMDE_FUNCTION_ATTRIBUTES
233+
simde__m128i
234+
simde_mm_mask_loadu_epi64(simde__m128i src, simde__mmask8 k, void const * mem_addr) {
235+
#if defined(SIMDE_X86_AVX512F_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE)
236+
return _mm_mask_loadu_epi64(src, k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
237+
#else
238+
return simde_mm_mask_mov_epi64(src, k, simde_mm_loadu_epi64(mem_addr));
239+
#endif
240+
}
241+
#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
242+
#undef _mm_mask_loadu_epi64
243+
#define _mm_mask_loadu_epi64(src, k, mem_addr) simde_mm_mask_loadu_epi64(src, k, mem_addr)
244+
#endif
245+
246+
SIMDE_FUNCTION_ATTRIBUTES
247+
simde__m128i
248+
simde_mm_maskz_loadu_epi64(simde__mmask8 k, void const * mem_addr) {
249+
#if defined(SIMDE_X86_AVX512F_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE)
250+
return _mm_maskz_loadu_epi64(k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
251+
#else
252+
return simde_mm_maskz_mov_epi64(k, simde_mm_loadu_epi64(mem_addr));
253+
#endif
254+
}
255+
#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
256+
#undef _mm_maskz_loadu_epi64
257+
#define _mm_maskz_loadu_epi64(k, mem_addr) simde_mm_maskz_loadu_epi64(k, mem_addr)
258+
#endif
259+
260+
SIMDE_FUNCTION_ATTRIBUTES
261+
simde__m128
262+
simde_mm_mask_loadu_ps(simde__m128 src, simde__mmask8 k, void const * mem_addr) {
263+
#if defined(SIMDE_X86_AVX512F_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE)
264+
return _mm_mask_loadu_ps(src, k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
265+
#else
266+
return simde_mm_mask_mov_ps(src, k, simde_mm_loadu_ps(HEDLEY_REINTERPRET_CAST(const float*, mem_addr)));
267+
#endif
268+
}
269+
#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
270+
#undef _mm_mask_loadu_ps
271+
#define _mm_mask_loadu_ps(src, k, mem_addr) simde_mm_mask_loadu_ps(src, k, mem_addr)
272+
#endif
273+
274+
SIMDE_FUNCTION_ATTRIBUTES
275+
simde__m128
276+
simde_mm_maskz_loadu_ps(simde__mmask8 k, void const * mem_addr) {
277+
#if defined(SIMDE_X86_AVX512F_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE)
278+
return _mm_maskz_loadu_ps(k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
279+
#else
280+
return simde_mm_maskz_mov_ps(k, simde_mm_loadu_ps(HEDLEY_REINTERPRET_CAST(const float*, mem_addr)));
281+
#endif
282+
}
283+
#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
284+
#undef _mm_maskz_loadu_ps
285+
#define _mm_maskz_loadu_ps(k, mem_addr) simde_mm_maskz_loadu_ps(k, mem_addr)
286+
#endif
287+
288+
SIMDE_FUNCTION_ATTRIBUTES
289+
simde__m128d
290+
simde_mm_mask_loadu_pd(simde__m128d src, simde__mmask8 k, void const * mem_addr) {
291+
#if defined(SIMDE_X86_AVX512F_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE)
292+
return _mm_mask_loadu_pd(src, k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
293+
#else
294+
return simde_mm_mask_mov_pd(src, k, simde_mm_loadu_pd(HEDLEY_REINTERPRET_CAST(const double*, mem_addr)));
295+
#endif
296+
}
297+
#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
298+
#undef _mm_mask_loadu_pd
299+
#define _mm_mask_loadu_pd(src, k, mem_addr) simde_mm_mask_loadu_pd(src, k, mem_addr)
300+
#endif
301+
302+
SIMDE_FUNCTION_ATTRIBUTES
303+
simde__m128d
304+
simde_mm_maskz_loadu_pd(simde__mmask8 k, void const * mem_addr) {
305+
#if defined(SIMDE_X86_AVX512F_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE)
306+
return _mm_maskz_loadu_pd(k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
307+
#else
308+
return simde_mm_maskz_mov_pd(k, simde_mm_loadu_pd(HEDLEY_REINTERPRET_CAST(const double*, mem_addr)));
309+
#endif
310+
}
311+
#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
312+
#undef _mm_maskz_loadu_pd
313+
#define _mm_maskz_loadu_pd(k, mem_addr) simde_mm_maskz_loadu_pd(k, mem_addr)
314+
#endif
315+
316+
SIMDE_FUNCTION_ATTRIBUTES
317+
simde__m256i
318+
simde_mm256_mask_loadu_epi16(simde__m256i src, simde__mmask16 k, void const * mem_addr) {
319+
#if defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE)
320+
return _mm256_mask_loadu_epi16(src, k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
321+
#else
322+
return simde_mm256_mask_mov_epi16(src, k, simde_mm256_loadu_epi16(mem_addr));
323+
#endif
324+
}
325+
#if defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
326+
#undef _mm256_mask_loadu_epi16
327+
#define _mm256_mask_loadu_epi16(src, k, mem_addr) simde_mm256_mask_loadu_epi16(src, k, mem_addr)
328+
#endif
329+
144330
SIMDE_FUNCTION_ATTRIBUTES
145331
simde__m256i
146-
simde_mm256_maskz_loadu_epi16 (simde__mmask16 k, void const * mem_addr) {
332+
simde_mm256_maskz_loadu_epi16(simde__mmask16 k, void const * mem_addr) {
147333
#if defined(SIMDE_X86_AVX512BW_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE)
148334
return _mm256_maskz_loadu_epi16(k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
149335
#else
@@ -155,6 +341,104 @@ simde_mm256_maskz_loadu_epi16 (simde__mmask16 k, void const * mem_addr) {
155341
#define _mm256_maskz_loadu_epi16(k, mem_addr) simde_mm256_maskz_loadu_epi16(k, mem_addr)
156342
#endif
157343

344+
SIMDE_FUNCTION_ATTRIBUTES
345+
simde__m256i
346+
simde_mm256_mask_loadu_epi32(simde__m256i src, simde__mmask8 k, void const * mem_addr) {
347+
#if defined(SIMDE_X86_AVX512F_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE)
348+
return _mm256_mask_loadu_epi32(src, k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
349+
#else
350+
return simde_mm256_mask_mov_epi32(src, k, simde_mm256_loadu_epi32(mem_addr));
351+
#endif
352+
}
353+
#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
354+
#undef _mm256_mask_loadu_epi32
355+
#define _mm256_mask_loadu_epi32(src, k, mem_addr) simde_mm256_mask_loadu_epi32(src, k, mem_addr)
356+
#endif
357+
358+
SIMDE_FUNCTION_ATTRIBUTES
359+
simde__m256i
360+
simde_mm256_maskz_loadu_epi32(simde__mmask8 k, void const * mem_addr) {
361+
#if defined(SIMDE_X86_AVX512F_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE)
362+
return _mm256_maskz_loadu_epi32(k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
363+
#else
364+
return simde_mm256_maskz_mov_epi32(k, simde_mm256_loadu_epi32(mem_addr));
365+
#endif
366+
}
367+
#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
368+
#undef _mm256_maskz_loadu_epi32
369+
#define _mm256_maskz_loadu_epi32(k, mem_addr) simde_mm256_maskz_loadu_epi32(k, mem_addr)
370+
#endif
371+
372+
SIMDE_FUNCTION_ATTRIBUTES
373+
simde__m256i
374+
simde_mm256_mask_loadu_epi64(simde__m256i src, simde__mmask8 k, void const * mem_addr) {
375+
#if defined(SIMDE_X86_AVX512F_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE)
376+
return _mm256_mask_loadu_epi64(src, k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
377+
#else
378+
return simde_mm256_mask_mov_epi64(src, k, simde_mm256_loadu_epi64(mem_addr));
379+
#endif
380+
}
381+
#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
382+
#undef _mm256_mask_loadu_epi64
383+
#define _mm256_mask_loadu_epi64(src, k, mem_addr) simde_mm256_mask_loadu_epi64(src, k, mem_addr)
384+
#endif
385+
386+
SIMDE_FUNCTION_ATTRIBUTES
387+
simde__m256i
388+
simde_mm256_maskz_loadu_epi64(simde__mmask8 k, void const * mem_addr) {
389+
#if defined(SIMDE_X86_AVX512F_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE)
390+
return _mm256_maskz_loadu_epi64(k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
391+
#else
392+
return simde_mm256_maskz_mov_epi64(k, simde_mm256_loadu_epi64(mem_addr));
393+
#endif
394+
}
395+
#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
396+
#undef _mm256_maskz_loadu_epi64
397+
#define _mm256_maskz_loadu_epi64(k, mem_addr) simde_mm256_maskz_loadu_epi64(k, mem_addr)
398+
#endif
399+
400+
SIMDE_FUNCTION_ATTRIBUTES
401+
simde__m256d
402+
simde_mm256_mask_loadu_pd (simde__m256d src, simde__mmask8 k, void const * mem_addr) {
403+
#if defined(SIMDE_X86_AVX512F_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE)
404+
return _mm256_mask_loadu_pd(src, k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
405+
#else
406+
return simde_mm256_mask_mov_pd(src, k, simde_mm256_loadu_pd(HEDLEY_REINTERPRET_CAST(const double*, mem_addr)));
407+
#endif
408+
}
409+
#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
410+
#undef _mm256_mask_loadu_pd
411+
#define _mm256_mask_loadu_pd(src, k, mem_addr) simde_mm256_mask_loadu_pd(src, k, mem_addr)
412+
#endif
413+
414+
SIMDE_FUNCTION_ATTRIBUTES
415+
simde__m256d
416+
simde_mm256_maskz_loadu_pd (simde__mmask8 k, void const * mem_addr) {
417+
#if defined(SIMDE_X86_AVX512F_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE)
418+
return _mm256_maskz_loadu_pd(k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
419+
#else
420+
return simde_mm256_maskz_mov_pd(k, simde_mm256_loadu_pd(HEDLEY_REINTERPRET_CAST(const double*, mem_addr)));
421+
#endif
422+
}
423+
#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
424+
#undef _mm256_maskz_loadu_pd
425+
#define _mm256_maskz_loadu_pd(k, mem_addr) simde_mm256_maskz_loadu_pd(k, mem_addr)
426+
#endif
427+
428+
SIMDE_FUNCTION_ATTRIBUTES
429+
simde__m256
430+
simde_mm256_mask_loadu_ps (simde__m256 src, simde__mmask8 k, void const * mem_addr) {
431+
#if defined(SIMDE_X86_AVX512F_NATIVE) && defined(SIMDE_X86_AVX512VL_NATIVE)
432+
return _mm256_mask_loadu_ps(src, k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
433+
#else
434+
return simde_mm256_mask_mov_ps(src, k, simde_mm256_loadu_ps(HEDLEY_REINTERPRET_CAST(const float*, mem_addr)));
435+
#endif
436+
}
437+
#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES) && defined(SIMDE_X86_AVX512VL_ENABLE_NATIVE_ALIASES)
438+
#undef _mm256_mask_loadu_ps
439+
#define _mm256_mask_loadu_ps(src, k, mem_addr) simde_mm256_mask_loadu_ps(src, k, mem_addr)
440+
#endif
441+
158442
SIMDE_FUNCTION_ATTRIBUTES
159443
simde__m256
160444
simde_mm256_maskz_loadu_ps (simde__mmask8 k, void const * mem_addr) {
@@ -169,6 +453,34 @@ simde_mm256_maskz_loadu_ps (simde__mmask8 k, void const * mem_addr) {
169453
#define _mm256_maskz_loadu_ps(k, mem_addr) simde_mm256_maskz_loadu_ps(k, mem_addr)
170454
#endif
171455

456+
SIMDE_FUNCTION_ATTRIBUTES
457+
simde__m512i
458+
simde_mm512_mask_loadu_epi8 (simde__m512i src, simde__mmask64 k, void const * mem_addr) {
459+
#if defined(SIMDE_X86_AVX512BW_NATIVE)
460+
return _mm512_mask_loadu_epi8(src, k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
461+
#else
462+
return simde_mm512_mask_mov_epi8(src, k, simde_mm512_loadu_epi8(mem_addr));
463+
#endif
464+
}
465+
#if defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
466+
#undef _mm512_mask_loadu_epi8
467+
#define _mm512_mask_loadu_epi8(src, k, mem_addr) simde_mm512_mask_loadu_epi8(src, k, mem_addr)
468+
#endif
469+
470+
SIMDE_FUNCTION_ATTRIBUTES
471+
simde__m512i
472+
simde_mm512_maskz_loadu_epi8 (simde__mmask64 k, void const * mem_addr) {
473+
#if defined(SIMDE_X86_AVX512BW_NATIVE)
474+
return _mm512_maskz_loadu_epi8(k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
475+
#else
476+
return simde_mm512_maskz_mov_epi8(k, simde_mm512_loadu_epi8(mem_addr));
477+
#endif
478+
}
479+
#if defined(SIMDE_X86_AVX512BW_ENABLE_NATIVE_ALIASES)
480+
#undef _mm512_maskz_loadu_epi8
481+
#define _mm512_maskz_loadu_epi8(k, mem_addr) simde_mm512_maskz_loadu_epi8(k, mem_addr)
482+
#endif
483+
172484
SIMDE_FUNCTION_ATTRIBUTES
173485
simde__m512i
174486
simde_mm512_mask_loadu_epi16 (simde__m512i src, simde__mmask32 k, void const * mem_addr) {
@@ -211,6 +523,21 @@ simde_mm512_mask_loadu_epi32 (simde__m512i src, simde__mmask16 k, void const * m
211523
#define _mm512_mask_loadu_epi32(src, k, mem_addr) simde_mm512_mask_loadu_epi32(src, k, mem_addr)
212524
#endif
213525

526+
SIMDE_FUNCTION_ATTRIBUTES
527+
simde__m512i
528+
simde_mm512_maskz_loadu_epi32 (simde__mmask16 k, void const * mem_addr) {
529+
#if defined(SIMDE_X86_AVX512F_NATIVE)
530+
return _mm512_maskz_loadu_epi32(k, HEDLEY_REINTERPRET_CAST(void const*, mem_addr));
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#else
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return simde_mm512_maskz_mov_epi32(k, simde_mm512_loadu_epi32(mem_addr));
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#endif
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}
535+
#if defined(SIMDE_X86_AVX512F_ENABLE_NATIVE_ALIASES)
536+
#undef _mm512_maskz_loadu_epi32
537+
#define _mm512_maskz_loadu_epi32(k, mem_addr) simde_mm512_maskz_loadu_epi32(k, mem_addr)
538+
#endif
539+
540+
214541
SIMDE_FUNCTION_ATTRIBUTES
215542
simde__m512i
216543
simde_mm512_mask_loadu_epi64 (simde__m512i src, simde__mmask8 k, void const * mem_addr) {

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