This can mainly be done by pulling in code from DragonPHY: https://github.com/StanfordVLSI/dragonphy2/blob/master/dragonphy/fpga_models/clk_delay_core.py
That delay is for a clock value signal (one cycle early), so it should probably be made more generic to handle both clock values and regular signals.
This can mainly be done by pulling in code from DragonPHY: https://github.com/StanfordVLSI/dragonphy2/blob/master/dragonphy/fpga_models/clk_delay_core.py
That delay is for a clock value signal (one cycle early), so it should probably be made more generic to handle both clock values and regular signals.