Update ci.yml

Author: scopeInfinity

.github/workflows/ci.yml

@@ -8,29 +8,21 @@ on:
 
 jobs:
   build:
-
     runs-on: ubuntu-latest
-
     steps:
     - uses: actions/checkout@v3
     - name: Set up Python
       uses: actions/setup-python@v5
       with:
         python-version: '3.x'
-    - name: install dependencies
+    - name: Install python dependencies
       run: |
-        sudo apt install nasm
         python -m pip install --upgrade pip
         pip install -r requirements.txt
-     - name: Install iverilog
-        run: |
-          git clone https://github.com/steveicarus/iverilog.git
-          cd iverilog
-          ./autogen.sh
-          ./configure
-          make
-          make install
-          cd ..
+    - name: Install iverilog
+      run:  |
+        sudo apt-get update
+        sudo apt-get install iverilog
     - name: make test
       run: make test
     - name: make

emulator/module/clock.v

@@ -51,5 +51,4 @@ module CLOCK(
 
     assign clk[0:3] = hw_clk[0:3];
     assign is_stage[0:3] = _is_stage[0:3];
-endmodule;
-
+endmodule

emulator/module/mblock/mblock.v

@@ -32,4 +32,4 @@ module MBLOCK(output[31:0] out,
     MUX_8_2 m2(.value(out[23:16]), .A(out0[23:16]), .B(out1[23:16]), .D(out3[23:16]), .S(selector[1:0]));
     MUX_8_2 m3(.value(out[31:24]), .A(out0[31:24]), .B(out1[31:24]), .D(out3[31:24]), .S(selector[1:0]));
 
-endmodule;
+endmodule

emulator/module/mblock/mconst.v

@@ -6,4 +6,4 @@ module MCONST(
     assign out[31:16] = 16'b0000000000000000;
     assign out[15:0] = in[15:0];
 
-endmodule;
+endmodule

emulator/module/mblock/ram.v

@@ -12,4 +12,4 @@ module RAM_32bit_16aline(output[31:0] out,
     end
     assign out = mem[address];
 
-endmodule;
+endmodule

emulator/module/mblock/rom.v

@@ -13,7 +13,7 @@ module _ROM_32bit_16aline(
 
     assign out = buffer[address];
 
-endmodule;
+endmodule
 
 module ROM_BOOT(
         output[31:0] out,
@@ -23,4 +23,4 @@ module ROM_BOOT(
     _ROM_32bit_16aline #(.filename("emulator/module/mblock/rom_boot.bin"))
         dut(.out(out),
         .address(address));
-endmodule;
+endmodule

emulator/module/mblock_mux.v

@@ -53,4 +53,4 @@ module MBLOCK_MUX(output[31:0] mblock_address,
     MUX_8_2 m2(.value(mblock_address[23:16]), .A(address0[23:16]), .B(address1[23:16]), ,C(address2[23:16]), .D(address3[23:16]), .S(mblock_selector[1:0]));
     MUX_8_2 m3(.value(mblock_address[31:24]), .A(address0[31:24]), .B(address1[31:24]), ,C(address2[31:24]), .D(address3[31:24]), .S(mblock_selector[1:0]));
 
-endmodule;
+endmodule

emulator/module/pc_next.v

@@ -34,5 +34,4 @@ module PC_NEXT(
         .out(program_counter),
         .in(program_counter_next),
         .clk(clk));
-endmodule;
-
+endmodule

emulator/module/stage0_ins_resolver.v

@@ -11,4 +11,4 @@ module INS_RESOLVER(output[7:0] v0, v1, v2, op,
     assign v2[7:0] = full_ins[23:16];
     assign op[7:0] = full_ins[31:24];
 
-endmodule;
+endmodule

emulator/module/stage1or2_store.v

@@ -4,4 +4,4 @@ module FETCH_AND_STORE(output[31:0] value,
 
     flipflop32 f(.out(value[31:0]), .in(in[31:0]), .clk(clk));
 
-endmodule;
+endmodule