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CAPI2 Syntax Gotcha: fileset_append existing fileset #767
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Description
Background
While converting to VCS 3-Step recently, I ran into a few file already defined error, despite the file only being defined once in the relevant fileset. I realized someone had extended a target and then appended a fileset that already existed in the base target. This was a simple syntax fix, but seems like it could be incorrect behavior.
Proposed Fix
I plan to implement either a parse error if this occurs, or a system which removes fileset duplication from within one core file. Will see which one fits better with the codebase, and if I automatically fix, add a warning that it occurred.
Example "Problem"
CAPI=2:
name: my:test:core
filesets:
files_rtl:
- dut.sv
file_type: systemVerilogSource
files_dv:
- tb.sv
file_type: systemVerilogSource
targets:
default: &default
filesets: [files_rtl]
sim_base: &sim_base:
<<: *default
filesets_append: [files_dv]
flow: sim
flow_options:
tool: vcs
toplevel: tb
unit_test:
<<: *sim_base
# issue occurs on next line
filesets_append: [files_dv]
parameters:
TESTNAME=unit_test
parameters:
TESTNAME:
datatype: string
paramtype: plusarg
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