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lint: verilator lint fixes for regfile common security module
1 parent 912c251 commit c15202c

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4 files changed

+43
-7
lines changed

4 files changed

+43
-7
lines changed

rtl/ibex_register_file_common.sv

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -8,17 +8,19 @@
88
*
99
* Register file common security functionality across multiple implementations
1010
*/
11+
1112
module ibex_register_file_common #(
1213
parameter bit FPGA = 0,
1314
parameter int unsigned AddrWidth = 5,
1415
parameter int unsigned NumWords = 2 ** AddrWidth,
15-
parameter int unsigned DataWidth = 32,
1616
parameter bit WrenCheck = 0,
1717
parameter bit RdataMuxCheck = 0
1818
) (
19+
/* verilator lint_off UNUSED */
1920
// Clock and Reset
2021
input logic clk_i,
2122
input logic rst_ni,
23+
/* verilator lint_on UNUSED */
2224

2325
//Read port R1
2426
input logic [4:0] raddr_a_i,
@@ -81,9 +83,9 @@ module ibex_register_file_common #(
8183
.err_o (oh_we_err)
8284
);
8385
end else begin : gen_no_wren_check
84-
if (FPGA == 0) begin : gen_unused_we0_strobe
85-
logic unused_strobe;
86-
assign unused_strobe = we_onehot_a[0]; // this is never read from in this case
86+
if (FPGA) begin : gen_unused_wren_check
87+
logic unused_waddr_a;
88+
assign unused_waddr_a = ^waddr_a_i;
8789
end
8890
assign oh_we_err = 1'b0;
8991
end
@@ -159,6 +161,11 @@ module ibex_register_file_common #(
159161
end else begin : gen_no_rdata_mux_check
160162
assign oh_raddr_a_err = 1'b0;
161163
assign oh_raddr_b_err = 1'b0;
164+
assign raddr_onehot_a = '0;
165+
assign raddr_onehot_b = '0;
166+
167+
logic unused_raddr;
168+
assign unused_raddr = ^{raddr_a_i, raddr_b_i};
162169
end
163170

164171
assign err_o = oh_raddr_a_err || oh_raddr_b_err || oh_we_err;

rtl/ibex_register_file_ff.sv

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,6 @@ module ibex_register_file_ff #(
5959
ibex_register_file_common #(
6060
.AddrWidth(ADDR_WIDTH),
6161
.NumWords(NUM_WORDS),
62-
.DataWidth(DataWidth),
6362
.WrenCheck(WrenCheck),
6463
.RdataMuxCheck(RdataMuxCheck)
6564
) security_module (
@@ -148,10 +147,21 @@ module ibex_register_file_ff #(
148147
end else begin : gen_no_rdata_mux_check
149148
assign rdata_a_o = rf_reg[raddr_a_i];
150149
assign rdata_b_o = rf_reg[raddr_b_i];
150+
151+
logic unused_raddr_onehot, unused_oh_raddr_err;
152+
assign unused_raddr_onehot = ^{raddr_onehot_a, raddr_onehot_b};
153+
assign unused_oh_raddr_err = ^{oh_raddr_a_err, oh_raddr_b_err};
151154
end
152155

153156
// Signal not used in FF register file
154157
logic unused_test_en;
155158
assign unused_test_en = test_en_i;
156159

160+
if (WrenCheck) begin : gen_wren_check
161+
end else begin : gen_unused_wren_check
162+
logic unused_strobe, unused_oh_we_err;
163+
assign unused_strobe = we_onehot_a[0]; // this is never read from in this case
164+
assign unused_oh_we_err = oh_we_err; // this is never read from in this case
165+
end
166+
157167
endmodule

rtl/ibex_register_file_fpga.sv

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,6 @@ module ibex_register_file_fpga #(
6161
.FPGA(1),
6262
.AddrWidth(ADDR_WIDTH),
6363
.NumWords(NUM_WORDS),
64-
.DataWidth(DataWidth),
6564
.WrenCheck(WrenCheck),
6665
.RdataMuxCheck(RdataMuxCheck)
6766
) security_module (
@@ -109,6 +108,10 @@ module ibex_register_file_fpga #(
109108
end else begin : gen_no_rdata_mux_check
110109
assign rdata_a_o = (raddr_a_i == '0) ? WordZeroVal : mem[raddr_a_i];
111110
assign rdata_b_o = (raddr_b_i == '0) ? WordZeroVal : mem[raddr_b_i];
111+
112+
logic unused_raddr_onehot, unused_oh_raddr_err;
113+
assign unused_raddr_onehot = ^{raddr_onehot_a, raddr_onehot_b};
114+
assign unused_oh_raddr_err = ^{oh_raddr_a_err, oh_raddr_b_err};
112115
end
113116

114117
// we select
@@ -143,4 +146,10 @@ module ibex_register_file_fpga #(
143146
logic unused_test_en;
144147
assign unused_test_en = test_en_i;
145148

149+
if (WrenCheck) begin : gen_wren_check
150+
end else begin : gen_unused_wren_check
151+
logic unused_oh_we_err;
152+
assign unused_oh_we_err = oh_we_err; // this is never read from in this case
153+
end
154+
146155
endmodule

rtl/ibex_register_file_latch.sv

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -71,7 +71,6 @@ module ibex_register_file_latch #(
7171
ibex_register_file_common #(
7272
.AddrWidth(ADDR_WIDTH),
7373
.NumWords(NUM_WORDS),
74-
.DataWidth(DataWidth),
7574
.WrenCheck(WrenCheck),
7675
.RdataMuxCheck(RdataMuxCheck)
7776
) security_module (
@@ -119,6 +118,10 @@ module ibex_register_file_latch #(
119118
end else begin : gen_no_rdata_mux_check
120119
assign rdata_a_o = mem[raddr_a_int];
121120
assign rdata_b_o = mem[raddr_b_int];
121+
122+
logic unused_raddr_onehot, unused_oh_raddr_err;
123+
assign unused_raddr_onehot = ^{raddr_onehot_a, raddr_onehot_b};
124+
assign unused_oh_raddr_err = ^{oh_raddr_a_err, oh_raddr_b_err};
122125
end
123126

124127
///////////
@@ -200,6 +203,13 @@ module ibex_register_file_latch #(
200203
assign mem[0] = WordZeroVal;
201204
end
202205

206+
if (WrenCheck) begin : gen_wren_check
207+
end else begin : gen_unused_wren_check
208+
logic unused_strobe, unused_oh_we_err;
209+
assign unused_strobe = we_onehot_a[0]; // this is never read from in this case
210+
assign unused_oh_we_err = oh_we_err; // this is never read from in this case
211+
end
212+
203213
`ifdef VERILATOR
204214
initial begin
205215
$display("Latch-based register file not supported for Verilator simulation");

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