diff --git a/JLCPCB/JLCPCB.kicad_dru b/JLCPCB/JLCPCB.kicad_dru index c42eb3c..1bee9a8 100644 --- a/JLCPCB/JLCPCB.kicad_dru +++ b/JLCPCB/JLCPCB.kicad_dru @@ -19,115 +19,201 @@ # TODO new rule: non-plated slots: min diameter/width 1.0mm # JLCPCB: "The minimum Non-Plated Slot Width is 1.0mm, please draw the slot outline in the mechanical layer(GML or GKO)"" -(rule "Track width, outer layer (1oz copper)" - (layer outer) - (condition "A.Type == 'track'") - (constraint track_width (min 0.127mm)) + +# --- Drill/Hole Size --- + +(rule "Drill Hole Size" + # Choose between: + # 1-2 Layers + # (constraint hole_size (min 0.3mm) (max 6.3mm)) + # 4-6 Layers (more costly) + # (constraint hole_size (min 0.15mm) (max 6.3mm)) + # 4-6 Layers (preferred) + (constraint hole_size (min 0.2mm) (max 6.3mm)) ) -(rule "Track spacing, outer layer (1oz copper)" - (layer outer) - (condition "A.Type == 'track' && B.Type == A.Type") - (constraint clearance (min 0.127mm)) +(rule "Via Hole Size" + (condition "A.Type == 'Via'") + # Choose between: + # 1-2 Layers + # (constraint hole_size (min 0.3mm)) + # 4-6 Layers (more costly) + # (constraint hole_size (min 0.15mm)) + # 4-6 Layers (preferred) + (constraint hole_size (min 0.2mm)) ) -(rule "Track width, inner layer" - (layer inner) - (condition "A.Type == 'track'") - (constraint track_width (min 0.09mm)) +(rule "Via Annular Ring" + (condition "A.Type == 'Via'") + # Choose between: + # 1-6 Layers + # (constraint annular_width (min 0.05mm)) + # 1-6 Layers (preferred) + (constraint annular_width (min 0.075mm)) ) -(rule "Track spacing, inner layer" - (layer inner) - (condition "A.Type == 'track' && B.Type == A.Type") - (constraint clearance (min 0.09mm)) +(rule "PTH Hole Size" + (condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && A.isPlated()") + (constraint hole_size (min 0.2mm) (max 6.3mm)) ) -(rule "Silkscreen text" - (layer "?.Silkscreen") - (condition "A.Type == 'Text' || A.Type == 'Text Box'") - (constraint text_thickness (min 0.15mm)) - (constraint text_height (min 1mm)) +(rule "NPTH Hole Size" + (condition "A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical' && !A.isPlated()") + (constraint hole_size (min 0.5mm)) ) -(rule "Pad to Silkscreen" +# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm. +(rule "Castellated Hole Size" (layer outer) - (condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'") - (constraint silk_clearance (min 0.15mm)) + (condition "A.Type == 'Pad' && A.Fabrication_Property == 'Castellated pad'") + (constraint hole (min 0.6mm)) ) -(rule "Edge (routed) to track clearance" - (condition "A.Type == 'track'") - (constraint edge_clearance (min 0.3mm)) +(rule "PTH Annular Ring" + (condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && A.isPlated()") + (constraint annular_width (min 0.075mm)) ) -#(rule "Edge (v-cut) to track clearance" -# (condition "A.Type == 'track'") -# (constraint edge_clearance (min 0.4mm)) -#) +(rule "NPTH Annular Ring" + (condition "A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical' && !A.isPlated()") + (constraint annular_width (min 0.25mm)) +) -# JLCPCB restrictions ambiguous: -# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)" -# This rule handles diameter minimum and maximum for ALL holes. -# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH) -(rule "Hole diameter" - (constraint hole_size (min 0.2mm) (max 6.3mm)) +# An expensive 4-Wire Kelvin Test is automatically added for holes that are < 0.3mm with a diameter ≤ 0.4mm. +(rule "Avoid 4-Wire Kelvin Test" + (condition "(A.Type == 'Via' && A.Hole < 0.3mm && A.Diameter <= 0.4mm) || (A.Type == 'Pad' && ((A.Hole_Size_X < 0.3mm && A.Size_X <= 0.4mm) || (A.Hole_Size_Y < 0.3mm && A.Size_Y <= 0.4mm)))") + # 4-6 Layers + (constraint annular_width (min 0.125mm)) ) -(rule "Hole (NPTH) diameter" - (layer outer) - (condition "!A.isPlated()") - (constraint hole_size (min 0.5mm)) + +# --- Minimum Clearance --- + +(rule "Hole to Hole Clearance (Different Nets)" + (condition "A.Net != B.Net") + (constraint hole_to_hole (min 0.5mm)) ) -# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm -(rule "Hole (castellated) diameter" - (layer outer) - (condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'") - (constraint hole_size (min 0.6mm)) +(rule "Via Hole to Via Hole Clearance (Same Net)" + (condition "A.Type == 'Via' && B.Type == 'Via' && A.Net == B.Net") + (constraint hole_to_hole (min 0.254mm)) ) -# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions) -# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production." -(rule "Annular ring width (via and PTH)" - (layer outer) - (condition "A.isPlated()") - (constraint annular_width (min 0.075mm)) +(rule "Pad to Pad Clearance (Pad without Hole, Different Nets)" + (condition "A.Type == 'Pad' && (A.Pad_Type != 'Through-hole' && A.Pad_Type != 'NPTH, mechanical') && B.Type == 'Pad' && (B.Pad_Type != 'Through-hole' && B.Pad_Type != 'NPTH, mechanical') && && A.Net != B.Net") + (constraint clearance (min 0.127mm)) ) -(rule "Clearance: hole to hole (perimeter), different nets" - (layer outer) - (condition "A.Net != B.Net") +(rule "Pad Hole to Pad Hole Clearance (Pad with Hole, Different Nets)" + (condition "A.Type == 'Pad' && (A.Pad_Type == 'Through-hole' || A.Pad_Type == 'NPTH, mechanical') && B.Type == 'Pad' && (B.Pad_Type == 'Through-hole' || B.Pad_Type == 'NPTH, mechanical') && && A.Net != B.Net") (constraint hole_to_hole (min 0.5mm)) ) -(rule "Clearance: hole to hole (perimeter), same net" - (layer outer) - (condition "A.Net == B.Net") +# NOTE: This is not stated specifically, but is implied by other rules. +(rule "Via/Pad to Via/Pad Clearance (Different Nets)" + (condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net") + (constraint clearance (min 0.127mm)) +) + +# NOTE: This is not stated specifically, but is implied by other rules. +(rule "Via/Pad Hole to Via/Pad Hole Clearance (Same Net)" + (condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net == B.Net") (constraint hole_to_hole (min 0.254mm)) ) -(rule "Clearance: track to NPTH hole (perimeter)" -# (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net") - (condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net") +(rule "Via to Trace" + (condition "A.Type == 'Via' && B.Type == 'Track'") (constraint hole_clearance (min 0.254mm)) ) -(rule "Clearance: track to PTH hole perimeter" - (condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net") +(rule "PTH to Trace" + (condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && A.isPlated() && B.Type == 'Track'") (constraint hole_clearance (min 0.33mm)) ) -# TODO: try combining with rule "Clearance: PTH to track, different nets" -(rule "Clearance: track to pad" - (condition "A.Type == 'pad' && B.Type == 'track' && A.Net != B.Net") +(rule "NPTH to Trace" + (condition "A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical' && !A.isPlated() && B.Type == 'Track'") + (constraint hole_clearance (min 0.254mm)) +) + +(rule "Pad to Trace" + (condition "A.Type == 'Pad' && (A.Pad_Type == 'Through-hole' || A.Pad_Type == 'NPTH, mechanical') && B.Type == 'Track' && A.Net != B.Net") (constraint clearance (min 0.2mm)) ) -(rule "Clearance: pad/via to pad/via" + +# --- Minimum Trace Width and Spacing --- + +(rule "Trace Width (Outer Layer)" (layer outer) -# (condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net") - (condition "A.isPlated() && B.isPlated() && A.Net != B.Net") - (constraint clearance (min 0.127mm)) + (condition "A.Type == 'Track'") + # Choose between: + # 1-2 Layers (1oz) + # (constraint track_width (min 0.127mm)) + # 4-6 Layers (1oz and 0.5oz) + (constraint track_width (min 0.09mm)) + # 1-6 Layers (2oz) + # (constraint track_width (min 0.2mm)) +) +(rule "Trace Spacing (Outer Layer)" + (layer outer) + (condition "A.Type == 'Track' && B.Type == 'Track'") + # Choose between: + # 1-2 Layers (1oz) + # (constraint clearance (min 0.127mm)) + # 4-6 Layers (1oz and 0.5oz) + (constraint clearance (min 0.09mm)) + # 1-6 Layers (2oz) + # (constraint clearance (min 0.2mm)) +) + +(rule "Trace Width (Inner Layer)" + (layer inner) + (condition "A.Type == 'Track'") + # Choose between: + # 4-6 Layers (1oz and 0.5oz) + (constraint track_width (min 0.09mm)) + # 4-6 Layers (2oz) + # (constraint track_width (min 0.2mm)) +) +(rule "Trace Spacing (Inner Layer)" + (layer inner) + (condition "A.Type == 'Track' && B.Type == 'Track'") + # Choose between: + # 4-6 Layers (1oz and 0.5oz) + (constraint clearance (min 0.09mm)) + # 4-6 Layers (2oz) + # (constraint clearance (min 0.2mm)) +) + + +# --- Legend --- + +(rule "Minimum Line Width" + (layer "?.Silkscreen") + (condition "A.Type == 'Text' || A.Type == 'Text Box'") + (constraint text_thickness (min 0.15mm)) ) +(rule "Minimum Text Height" + (layer "?.Silkscreen") + (condition "A.Type == 'Text' || A.Type == 'Text Box'") + (constraint text_height (min 1mm)) +) + +(rule "Pad to Silkscreen" + (condition "A.Type == 'Pad' && ((A.existsOnLayer('F.Mask') && B.Layer == 'F.Silkscreen') || (A.existsOnLayer('B.Mask') && B.Layer == 'B.Silkscreen')) ") + (constraint silk_clearance (min 0.15mm)) +) + + +# --- Board Outlines --- + +(rule "Trace to Board Edge" + (condition "A.Type == 'Track'") + # Choose between: + # Routed + (constraint edge_clearance (min 0.3mm)) + # V-Cut Panel + # (constraint edge_clearance (min 0.4mm)) +) diff --git a/JLCPCB/JLCPCB.kicad_pcb b/JLCPCB/JLCPCB.kicad_pcb index 79309c8..149c3be 100644 --- a/JLCPCB/JLCPCB.kicad_pcb +++ b/JLCPCB/JLCPCB.kicad_pcb @@ -114,7 +114,7 @@ (at 143 79) (descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator") (tags "resistor") - (attr smd) + (attr smd board_only) (fp_text reference "REF**" (at 0 -1.65) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15))) (tstamp 6fc21dea-6dac-430c-945e-5ed91dfbdbae) @@ -195,7 +195,7 @@ (effects (font (size 1 1) (thickness 0.15))) (tstamp 49e5a99f-d43d-48aa-8a5d-5e832cba2cc1) ) - (pad "1" thru_hole circle (at 0 0) (size 7.4 7.4) (drill 6.4) (layers "*.Cu" "*.Mask") (tstamp 3de95e5c-bbca-4895-b9c7-91770b6ebb39)) + (pad "1" thru_hole circle (at 0 0) (size 7.4 7.4) (drill 6.31) (layers "*.Cu" "*.Mask") (tstamp 3de95e5c-bbca-4895-b9c7-91770b6ebb39)) ) (footprint "MountingHole:MountingHole_2.2mm_M2_DIN965_Pad_TopBottom" (layer "F.Cu") @@ -242,6 +242,21 @@ (net 1 "+5V") (tstamp 524c74fc-eb91-418e-af2d-ea0edda34bf3)) ) + (footprint "" (layer "F.Cu") + (tstamp 4faa5a5e-b0d9-4fa9-9132-87d32c1c48b6) + (at 143.95 126.63) + (fp_text reference "" (at 0 0) (layer "F.SilkS") + (effects (font (size 1.27 1.27) (thickness 0.15))) + (tstamp bcbcb399-af2f-4076-8cc4-6dc3de6dc938) + ) + (fp_text value "" (at 0 0) (layer "F.SilkS") + (effects (font (size 1.27 1.27) (thickness 0.15))) + (tstamp a212801c-b169-456f-b293-c94fe0928ac8) + ) + (pad "" thru_hole rect (at 0.05 -0.13) (size 0.45 0.45) (drill 0.2) (layers "*.Cu" "*.Mask") + (pinfunction "VCC") (pintype "passive") (tstamp e37f0f3a-fef6-44fa-a3ca-468c2ff9288c)) + ) + (footprint "MountingHole:MountingHole_2.2mm_M2_DIN965_Pad_TopBottom" (layer "F.Cu") (tstamp 581fa8cc-3dc3-43fc-bda1-88c961d747d2) (at 128 119) @@ -260,7 +275,22 @@ (effects (font (size 1 1) (thickness 0.15))) (tstamp 1f3177c9-4d56-4e1b-8148-4b1629e9a315) ) - (pad "1" thru_hole circle (at 0 0) (size 1 1) (drill 0.5) (property pad_prop_castellated) (layers "*.Cu" "*.Mask") (tstamp a9a2445f-cf30-4e10-8f11-6156f08505da)) + (pad "1" thru_hole circle (at 0 0) (size 1 1) (drill 0.59) (property pad_prop_castellated) (layers "*.Cu" "*.Mask") (tstamp a9a2445f-cf30-4e10-8f11-6156f08505da)) + ) + + (footprint "" (layer "F.Cu") + (tstamp 58e211ac-fe95-40bc-90f6-59b6c476157c) + (at 143.01 126.63) + (fp_text reference "" (at 0 0) (layer "F.SilkS") + (effects (font (size 1.27 1.27) (thickness 0.15))) + (tstamp 93da58cd-40d4-4e48-92e1-8bf84c6e5506) + ) + (fp_text value "" (at 0 0) (layer "F.SilkS") + (effects (font (size 1.27 1.27) (thickness 0.15))) + (tstamp 9029c7b2-b9e8-4033-83d4-7e166bb28457) + ) + (pad "" thru_hole circle (at -0.01 -0.13) (size 0.45 0.45) (drill 0.2) (layers "*.Cu" "*.Mask") + (pinfunction "VCC") (pintype "passive") (tstamp e37f0f3a-fef6-44fa-a3ca-468c2ff9288c)) ) (footprint "MountingHole:MountingHole_2.2mm_M2_DIN965_Pad_TopBottom" (layer "F.Cu") @@ -285,6 +315,21 @@ (net 1 "+5V") (tstamp 7c1454ee-91d8-4166-b329-a7ac4e94cc52)) ) + (footprint "" (layer "F.Cu") + (tstamp 614ac1c0-b8ea-432e-a2de-04fdb4579167) + (at 120.99 187 90) + (fp_text reference "" (at 0 0 90) (layer "F.SilkS") + (effects (font (size 1.27 1.27) (thickness 0.15))) + (tstamp ee8b28e1-b788-4b18-8434-c23242c8adc4) + ) + (fp_text value "" (at 0 0 90) (layer "F.SilkS") + (effects (font (size 1.27 1.27) (thickness 0.15))) + (tstamp ad130f53-ba5a-4388-b1ec-1724a4e02923) + ) + (pad "2" smd roundrect (at 0.126 -0.09 90) (size 2 2) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) + (net 2 "GND") (tstamp 85846a52-51ec-4dcb-b192-4f2068d89633)) + ) + (footprint "Connector_Pin:Pin_D0.7mm_L6.5mm_W1.8mm_FlatFork" (layer "F.Cu") (tstamp 670f0cc0-91cc-409e-a480-26ebbba3e311) (at 123 159.8) @@ -346,7 +391,7 @@ (effects (font (size 1 1) (thickness 0.15))) (tstamp d8b5b8b8-282e-429d-9d4d-c936a62344c6) ) - (pad "" np_thru_hole circle (at 0 0) (size 1 1) (drill 0.45) (layers "F&B.Cu" "*.Mask") (tstamp fa673693-8feb-4dab-b89f-312fade5b2b4)) + (pad "" np_thru_hole circle (at 0 0) (size 1 1) (drill 0.49) (layers "F&B.Cu" "*.Mask") (tstamp fa673693-8feb-4dab-b89f-312fade5b2b4)) ) (footprint "Resistor_SMD:R_0805_2012Metric" (layer "F.Cu") @@ -354,7 +399,7 @@ (at 121 79) (descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator") (tags "resistor") - (attr smd) + (attr smd board_only) (fp_text reference "REF**" (at 0 -1.65) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15))) (tstamp 8df62fe0-c0f9-471b-8880-86339c52b7a7) @@ -462,6 +507,21 @@ (net 2 "GND") (tstamp b52a9292-661d-4f2d-acbb-4483d0c3b986)) ) + (footprint "" (layer "F.Cu") + (tstamp 97a0be44-9bef-49fb-9136-6771a1f6ca05) + (at 145.09 187) + (fp_text reference "" (at 0 0) (layer "F.SilkS") + (effects (font (size 1.27 1.27) (thickness 0.15))) + (tstamp e7b48fad-c05a-47e9-9d0f-6a2641c2ac4a) + ) + (fp_text value "" (at 0 0) (layer "F.SilkS") + (effects (font (size 1.27 1.27) (thickness 0.15))) + (tstamp 651e95da-a1f9-441c-9731-c6878eb94715) + ) + (pad "2" smd roundrect (at 0.06 -0.127 90) (size 2 2) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) + (net 2 "GND") (tstamp 800a6470-64f3-4898-b3f2-99a32ba59c3d)) + ) + (footprint "MountingHole:MountingHole_2.2mm_M2_DIN965_Pad_TopBottom" (layer "F.Cu") (tstamp 9836f411-f3bb-427c-bd98-de881c58d3ca) (at 145.15 189) @@ -502,7 +562,7 @@ (effects (font (size 1 1) (thickness 0.15))) (tstamp f7b29376-2005-448e-8a70-405f4ff48254) ) - (pad "1" thru_hole circle (at 0 0) (size 2 2) (drill 1) (property pad_prop_castellated) (layers "*.Cu" "*.Mask") + (pad "1" thru_hole circle (at 0 0) (size 2 2) (drill 1) (layers "*.Cu" "*.Mask") (net 2 "GND") (tstamp 7d07f0d2-3a0a-472b-94e9-af4b08572d67)) ) @@ -568,7 +628,7 @@ (effects (font (size 1 1) (thickness 0.15))) (tstamp 2ec28b3e-d377-4b48-b87a-7bad41752491) ) - (pad "1" thru_hole circle (at 0 0) (size 2 2) (drill 1) (property pad_prop_castellated) (layers "*.Cu" "*.Mask") + (pad "1" thru_hole circle (at 0 0) (size 2 2) (drill 1) (layers "*.Cu" "*.Mask") (net 1 "+5V") (tstamp 27dcb0d0-4c1d-4e32-a14d-ea0ee41357f4)) ) @@ -590,8 +650,22 @@ (effects (font (size 1 1) (thickness 0.15))) (tstamp 154f371e-6231-4fca-8627-5abbb2779ca0) ) - (pad "1" thru_hole circle (at 0 0) (size 1 1) (drill 0.9) (property pad_prop_castellated) (layers "*.Cu" "*.Mask") - (net 2 "GND") (tstamp e913ab81-6a2e-4c98-b2e5-1576e81399ff)) + (pad "1" thru_hole circle (at 0 0) (size 1 1) (drill 0.86) (property pad_prop_castellated) (layers "*.Cu" "*.Mask") (tstamp e913ab81-6a2e-4c98-b2e5-1576e81399ff)) + ) + + (footprint "" (layer "F.Cu") + (tstamp d783a6c5-271f-4717-8b2a-cfd59bb81cff) + (at 119 126.5) + (fp_text reference "" (at 0 0) (layer "F.SilkS") + (effects (font (size 1.27 1.27) (thickness 0.15))) + (tstamp ad3c321b-42e0-44fe-a4a5-c1b707ac4884) + ) + (fp_text value "" (at 0 0) (layer "F.SilkS") + (effects (font (size 1.27 1.27) (thickness 0.15))) + (tstamp dec7bcb0-3214-4e78-967a-3b5088e1e9bb) + ) + (pad "" thru_hole circle (at 0 0) (size 0.4 0.4) (drill 0.2) (layers "*.Cu" "*.Mask") + (pinfunction "VCC") (pintype "passive") (tstamp e37f0f3a-fef6-44fa-a3ca-468c2ff9288c)) ) (footprint "MountingHole:MountingHole_2.2mm_M2_DIN965_Pad_TopBottom" (layer "F.Cu") @@ -612,7 +686,7 @@ (effects (font (size 1 1) (thickness 0.15))) (tstamp 99a9b29c-4018-4ee0-abe5-8ac1099f2a93) ) - (pad "1" thru_hole circle (at 0 0) (size 0.6 0.6) (drill 0.15) (layers "*.Cu" "*.Mask") (tstamp 85636039-c380-4883-9002-5f0f2f5e5fe5)) + (pad "1" thru_hole circle (at 0 0) (size 0.6 0.6) (drill 0.19) (layers "*.Cu" "*.Mask") (tstamp 85636039-c380-4883-9002-5f0f2f5e5fe5)) ) (footprint "MountingHole:MountingHole_3.5mm_Pad_TopBottom" (layer "F.Cu") @@ -633,7 +707,7 @@ (effects (font (size 1 1) (thickness 0.15))) (tstamp b8268f69-2202-4734-b6e3-f15ea354c1f7) ) - (pad "1" thru_hole circle (at 0 0) (size 7.3 7.3) (drill 6.3) (layers "*.Cu" "*.Mask") (tstamp 1fc084df-da74-4cb1-a44e-5cda646fabab)) + (pad "1" thru_hole circle (at 0 0) (size 7.4 7.4) (drill 6.3) (layers "*.Cu" "*.Mask") (tstamp 1fc084df-da74-4cb1-a44e-5cda646fabab)) ) (footprint "MountingHole:MountingHole_2.1mm" (layer "F.Cu") @@ -654,7 +728,7 @@ (effects (font (size 1 1) (thickness 0.15))) (tstamp bde4ac3e-d72a-4156-b0dd-ba68a9de1455) ) - (pad "" np_thru_hole circle (at 0 0) (size 1 1) (drill 0.55) (layers "F&B.Cu" "*.Mask") (tstamp ffee830e-e440-4ef3-9cf1-a25418e5642d)) + (pad "" np_thru_hole circle (at 0 0) (size 1 1) (drill 0.5) (layers "F&B.Cu" "*.Mask") (tstamp ffee830e-e440-4ef3-9cf1-a25418e5642d)) ) (footprint "MountingHole:MountingHole_2.2mm_M2_DIN965_Pad_TopBottom" (layer "F.Cu") @@ -719,8 +793,22 @@ (effects (font (size 1 1) (thickness 0.15))) (tstamp df12efcf-67ef-4ec4-8746-0c3661afb415) ) - (pad "1" thru_hole circle (at 0 0) (size 1 1) (drill 0.85) (property pad_prop_castellated) (layers "*.Cu" "*.Mask") - (net 2 "GND") (tstamp fe783d36-0b0f-4e02-b47f-9c8b1cae8e73)) + (pad "1" thru_hole circle (at 0 0) (size 1 1) (drill 0.85) (property pad_prop_castellated) (layers "*.Cu" "*.Mask") (tstamp fe783d36-0b0f-4e02-b47f-9c8b1cae8e73)) + ) + + (footprint "" (layer "F.Cu") + (tstamp fc7c976c-7fbb-43dd-b087-9976896c77c7) + (at 120 126.5) + (fp_text reference "" (at 0 0) (layer "F.SilkS") + (effects (font (size 1.27 1.27) (thickness 0.15))) + (tstamp 6df69156-1172-4b2c-85eb-2f41fece3195) + ) + (fp_text value "" (at 0 0) (layer "F.SilkS") + (effects (font (size 1.27 1.27) (thickness 0.15))) + (tstamp 856c2066-aa47-44b1-bf01-5a418ead323a) + ) + (pad "" thru_hole rect (at 0 0) (size 0.4 0.4) (drill 0.2) (layers "*.Cu" "*.Mask") + (pinfunction "VCC") (pintype "passive") (tstamp e37f0f3a-fef6-44fa-a3ca-468c2ff9288c)) ) (footprint "Resistor_THT:R_Axial_DIN0204_L3.6mm_D1.6mm_P2.54mm_Vertical" (layer "F.Cu") @@ -773,10 +861,10 @@ ) ) - (gr_rect (start 122.6 78) (end 125 80) - (stroke (width 0.15) (type default)) (fill none) (layer "F.SilkS") (tstamp 0153a69a-9eef-4edb-8fb4-57ec74e0d1e2)) - (gr_rect (start 139 78) (end 141.293082 80) - (stroke (width 0.15) (type default)) (fill none) (layer "F.SilkS") (tstamp cf9fe686-83b2-4ae4-901c-eaf2514c482a)) + (gr_rect (start 122.57 78) (end 123 80) + (stroke (width 0) (type solid)) (fill solid) (layer "F.SilkS") (tstamp 53c4aca4-e26d-41ac-a52e-ad4657d201bb)) + (gr_rect (start 144.58 78) (end 145 80) + (stroke (width 0) (type solid)) (fill solid) (layer "F.SilkS") (tstamp 5c84acd7-0c35-4b9f-a1c0-2a4a6659eedc)) (gr_line (start 128 90) (end 128 88) (stroke (width 0.1) (type default)) (layer "Edge.Cuts") (tstamp 0e3e1ccc-7ffb-493b-92e0-9f90c301167f)) (gr_arc (start 135 90) (mid 134.707107 90.707107) (end 134 91) @@ -820,120 +908,119 @@ (gr_text "Too small" (at 115 58) (layer "F.SilkS") (tstamp 9e0cfe3a-e71a-4f93-8425-c479f42ab25e) (effects (font (size 0.9 1) (thickness 0.15)) (justify left bottom)) ) - (gr_text "Too\nnarrow!" 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"drill": 1.0, - "height": 2.0, - "width": 2.0 + "drill": 0.2, + "height": 0.45, + "width": 0.45 }, "silk_line_width": 0.15, "silk_text_italic": false, @@ -80,7 +80,7 @@ "item_on_disabled_layer": "error", "items_not_allowed": "error", "length_out_of_range": "error", - "lib_footprint_issues": "warning", + "lib_footprint_issues": "ignore", "lib_footprint_mismatch": "ignore", "malformed_courtyard": "error", "microvia_drill_out_of_range": "error", @@ -93,12 +93,12 @@ "shorting_items": "error", "silk_edge_clearance": "warning", "silk_over_copper": "warning", - "silk_overlap": "warning", + "silk_overlap": "error", "skew_out_of_range": "error", "solder_mask_bridge": "error", "starved_thermal": "error", - "text_height": "warning", - "text_thickness": "warning", + "text_height": "error", + "text_thickness": "error", "through_hole_pad_without_hole": "error", "too_many_vias": "error", "track_dangling": "ignore", @@ -116,12 +116,12 @@ "min_copper_edge_clearance": 0.0, "min_hole_clearance": 0.0, "min_hole_to_hole": 0.0, - "min_microvia_diameter": 0.19999999999999998, - "min_microvia_drill": 0.09999999999999999, + "min_microvia_diameter": 0.0, + "min_microvia_drill": 0.0, "min_resolved_spokes": 2, "min_silk_clearance": 0.0, - "min_text_height": 0.09999999999999999, - "min_text_thickness": 0.01, + "min_text_height": 0.0, + "min_text_thickness": 0.0, "min_through_hole_diameter": 0.508, "min_track_width": 0.0, "min_via_annular_width": 0.0,