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22= XtightlyCoupledIO
33Jan Oleksiewicz <jnk0le@hotmail.com>
4- :appversion: 3.2.54
4+ :appversion: 3.2.55
55:toc:
66:toclevels: 4
77:sectnums:
@@ -19,6 +19,7 @@ This document is released under a Creative Commons Attribution 4.0 International
1919[cols="1,5",options=header]
2020|====================================================================================
2121| Version | Change
22+ | v3.2.55 | added dspic
2223| v3.2.54 | rp2350 coprocessor instructions
2324| v3.2.53 | more improvements, IO by csr on esp32, extra avr8 note
2425| v3.2.52 | some text improvements
@@ -251,6 +252,16 @@ offers:
251252- instructions accessing only a single bit (bit position must be passed through register)
252253- double wide access (requires at least 3r2w regfile, already available in m33)
253254
255+ ==== dsPIC33 (16bit and 32bit)
256+
257+ offers CISC addressing modes to acces the peripheral SFRs
258+
259+ - indirect addressing mode where one source and destination register can be a pointer to SFR
260+ - direct addressing (aka "file register addressing") which can acces "near memory space"
261+ (8KiB on 16bit and 64KiB on 32bit ones)
262+
263+ Full set of bit and bitfield instructions. Bit can be extracted to status flags for branching.
264+
254265=== alternative approaches
255266
256267==== map to upper GPR
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