FPGA/Counter-issue.v at master · jbeale1/FPGA · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
// used to work....?
module count2
#( parameter WIDTH = 29 )
    (
    input wire clk50,
    output [7:0] LEDS
    );

reg [WIDTH:0] cnt;

always @(posedge clk50)
  begin
    cnt <= cnt+1;  // increment counter register on each clock
  end

assign LEDS = cnt[WIDTH:(WIDTH-7)];  // output 7 highest-order bits

endmodule


// below code has LED7 blinking at rate expected for LED0, all other LEDs remain off
module count2
#( parameter WIDTH = 29 )
    (
    input wire clk50,
    output [7:0] LEDS
    );

reg [WIDTH:0] cnt;
wire clk;  // clock signal

clkgen clkgen_inst (
         .CLK_IN1(clk50), // external 50 MHz clock from pin
         .CLK_OUT1(clk) ); // new clock signal

always @(posedge clk)
  begin
    cnt <= cnt+1;  // increment counter register on each clock
  end

assign LEDS = cnt[WIDTH:(WIDTH-7)];  // output 7 highest-order bits
endmodule

// ==================================================================
// this one works!

module counter1
#( parameter WIDTH = 30 )
    (input clk50, input ena1, output reg [7:0] LEDS );

reg [WIDTH:0] cnt;

wire clk;  // clock signal

clkgen clkgen_inst (
         .CLK_IN1(clk50), // external 50 MHz clock from pin
         .CLK_OUT1(clk) ); // new clock signal

always @(posedge clk)
  begin
    if (ena1) begin
      cnt <= cnt+1;
    end
  LEDS <= cnt[WIDTH:WIDTH-7];
  end
endmodule