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PTL: Release v1.04 event files
This commit releases PTL v1.04 events and updates mapfile.csv accordingly.
1 parent 2eebd8e commit 1f46fa2

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-21
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4 files changed

+291
-21
lines changed

‎PTL/events/pantherlake_cougarcove_core.json‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
{
22
"Header": {
3-
"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
4-
"Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.03",
5-
"DatePublished": "11/14/2025",
6-
"Version": "1.03",
3+
"Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
4+
"Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.04",
5+
"DatePublished": "01/23/2026",
6+
"Version": "1.04",
77
"Legend": ""
88
},
99
"Events": [

‎PTL/events/pantherlake_darkmont_core.json‎

Lines changed: 280 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
{
22
"Header": {
3-
"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
4-
"Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.03",
5-
"DatePublished": "11/14/2025",
6-
"Version": "1.03",
3+
"Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
4+
"Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.04",
5+
"DatePublished": "01/23/2026",
6+
"Version": "1.04",
77
"Legend": ""
88
},
99
"Events": [
@@ -39,8 +39,8 @@
3939
"UMask": "0x02",
4040
"UMaskExt": "0x00",
4141
"EventName": "CPU_CLK_UNHALTED.CORE",
42-
"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.",
43-
"PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.",
42+
"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
43+
"PublicDescription": "Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]",
4444
"Counter": "Fixed counter 1",
4545
"PEBScounters": "33",
4646
"SampleAfterValue": "2000003",
@@ -979,6 +979,33 @@
979979
"PDISTCounter": "NA",
980980
"Speculative": "1"
981981
},
982+
{
983+
"EventCode": "0x24",
984+
"UMask": "0xc8",
985+
"UMaskExt": "0x00",
986+
"EventName": "L2_REQUEST.HWPF",
987+
"BriefDescription": "Counts the number of L2 cache accesses from front door Hardware Prefetch requests. Does not include rejects or recycles, per core event.",
988+
"PublicDescription": "Counts the number of L2 cache accesses from front door Hardware Prefetch requests. Does not include rejects or recycles, per core event.",
989+
"Counter": "0,1,2,3,4,5,6,7",
990+
"PEBScounters": "0,1,2,3,4,5,6,7",
991+
"SampleAfterValue": "1000003",
992+
"MSRIndex": "0x00",
993+
"MSRValue": "0x00",
994+
"Precise": "0",
995+
"CollectPEBSRecord": "2",
996+
"TakenAlone": "0",
997+
"CounterMask": "0",
998+
"Invert": "0",
999+
"EdgeDetect": "0",
1000+
"Data_LA": "0",
1001+
"L1_Hit_Indication": "0",
1002+
"Errata": "null",
1003+
"Offcore": "0",
1004+
"Deprecated": "0",
1005+
"Equal": "0",
1006+
"PDISTCounter": "NA",
1007+
"Speculative": "1"
1008+
},
9821009
{
9831010
"EventCode": "0x24",
9841011
"UMask": "0xff",
@@ -2140,6 +2167,33 @@
21402167
"PDISTCounter": "NA",
21412168
"Speculative": "1"
21422169
},
2170+
{
2171+
"EventCode": "0x75",
2172+
"UMask": "0x08",
2173+
"UMaskExt": "0x00",
2174+
"EventName": "SERIALIZATION.COLOR_STALLS",
2175+
"BriefDescription": "Counts the number issue slots not consumed due to a color request for an FCW or MXCSR control register when all 4 colors (copies) are already in use.",
2176+
"PublicDescription": "Counts the number issue slots not consumed due to a color request for an FCW or MXCSR control register when all 4 colors (copies) are already in use.",
2177+
"Counter": "0,1,2,3,4,5,6,7",
2178+
"PEBScounters": "0,1,2,3,4,5,6,7",
2179+
"SampleAfterValue": "1000003",
2180+
"MSRIndex": "0x00",
2181+
"MSRValue": "0x00",
2182+
"Precise": "0",
2183+
"CollectPEBSRecord": "2",
2184+
"TakenAlone": "0",
2185+
"CounterMask": "0",
2186+
"Invert": "0",
2187+
"EdgeDetect": "0",
2188+
"Data_LA": "0",
2189+
"L1_Hit_Indication": "0",
2190+
"Errata": "null",
2191+
"Offcore": "0",
2192+
"Deprecated": "0",
2193+
"Equal": "0",
2194+
"PDISTCounter": "NA",
2195+
"Speculative": "1"
2196+
},
21432197
{
21442198
"EventCode": "0x80",
21452199
"UMask": "0x01",
@@ -3436,6 +3490,87 @@
34363490
"PDISTCounter": "0,1",
34373491
"Speculative": "0"
34383492
},
3493+
{
3494+
"EventCode": "0xc4",
3495+
"UMask": "0x01",
3496+
"UMaskExt": "0x00",
3497+
"EventName": "BR_INST_RETIRED.COND_TAKEN_BWD",
3498+
"BriefDescription": "Counts the number of taken backward conditional branch instructions retired.",
3499+
"PublicDescription": "Counts the number of taken backward conditional branch instructions retired.",
3500+
"Counter": "0,1,2,3,4,5,6,7",
3501+
"PEBScounters": "0,1,2,3,4,5,6,7",
3502+
"SampleAfterValue": "1000003",
3503+
"MSRIndex": "0x00",
3504+
"MSRValue": "0x00",
3505+
"Precise": "1",
3506+
"CollectPEBSRecord": "2",
3507+
"TakenAlone": "0",
3508+
"CounterMask": "0",
3509+
"Invert": "0",
3510+
"EdgeDetect": "0",
3511+
"Data_LA": "0",
3512+
"L1_Hit_Indication": "0",
3513+
"Errata": "null",
3514+
"Offcore": "0",
3515+
"Deprecated": "0",
3516+
"Equal": "0",
3517+
"PDISTCounter": "0,1",
3518+
"Speculative": "0"
3519+
},
3520+
{
3521+
"EventCode": "0xc4",
3522+
"UMask": "0x02",
3523+
"UMaskExt": "0x00",
3524+
"EventName": "BR_INST_RETIRED.COND_TAKEN_FWD",
3525+
"BriefDescription": "Counts the number of taken forward conditional branch instructions retired.",
3526+
"PublicDescription": "Counts the number of taken forward conditional branch instructions retired.",
3527+
"Counter": "0,1,2,3,4,5,6,7",
3528+
"PEBScounters": "0,1,2,3,4,5,6,7",
3529+
"SampleAfterValue": "1000003",
3530+
"MSRIndex": "0x00",
3531+
"MSRValue": "0x00",
3532+
"Precise": "1",
3533+
"CollectPEBSRecord": "2",
3534+
"TakenAlone": "0",
3535+
"CounterMask": "0",
3536+
"Invert": "0",
3537+
"EdgeDetect": "0",
3538+
"Data_LA": "0",
3539+
"L1_Hit_Indication": "0",
3540+
"Errata": "null",
3541+
"Offcore": "0",
3542+
"Deprecated": "0",
3543+
"Equal": "0",
3544+
"PDISTCounter": "0,1",
3545+
"Speculative": "0"
3546+
},
3547+
{
3548+
"EventCode": "0xc4",
3549+
"UMask": "0x03",
3550+
"UMaskExt": "0x00",
3551+
"EventName": "BR_INST_RETIRED.COND_TAKEN",
3552+
"BriefDescription": "Counts the number of taken conditional branch instructions retired.",
3553+
"PublicDescription": "Counts the number of taken conditional branch instructions retired.",
3554+
"Counter": "0,1,2,3,4,5,6,7",
3555+
"PEBScounters": "0,1,2,3,4,5,6,7",
3556+
"SampleAfterValue": "1000003",
3557+
"MSRIndex": "0x00",
3558+
"MSRValue": "0x00",
3559+
"Precise": "1",
3560+
"CollectPEBSRecord": "2",
3561+
"TakenAlone": "0",
3562+
"CounterMask": "0",
3563+
"Invert": "0",
3564+
"EdgeDetect": "0",
3565+
"Data_LA": "0",
3566+
"L1_Hit_Indication": "0",
3567+
"Errata": "null",
3568+
"Offcore": "0",
3569+
"Deprecated": "0",
3570+
"Equal": "0",
3571+
"PDISTCounter": "0,1",
3572+
"Speculative": "0"
3573+
},
34393574
{
34403575
"EventCode": "0xc4",
34413576
"UMask": "0x04",
@@ -3463,6 +3598,33 @@
34633598
"PDISTCounter": "0,1",
34643599
"Speculative": "0"
34653600
},
3601+
{
3602+
"EventCode": "0xc4",
3603+
"UMask": "0x07",
3604+
"UMaskExt": "0x00",
3605+
"EventName": "BR_INST_RETIRED.COND",
3606+
"BriefDescription": "Counts the number of conditional branch instructions retired.",
3607+
"PublicDescription": "Counts the number of conditional branch instructions retired.",
3608+
"Counter": "0,1,2,3,4,5,6,7",
3609+
"PEBScounters": "0,1,2,3,4,5,6,7",
3610+
"SampleAfterValue": "1000003",
3611+
"MSRIndex": "0x00",
3612+
"MSRValue": "0x00",
3613+
"Precise": "1",
3614+
"CollectPEBSRecord": "2",
3615+
"TakenAlone": "0",
3616+
"CounterMask": "0",
3617+
"Invert": "0",
3618+
"EdgeDetect": "0",
3619+
"Data_LA": "0",
3620+
"L1_Hit_Indication": "0",
3621+
"Errata": "null",
3622+
"Offcore": "0",
3623+
"Deprecated": "0",
3624+
"Equal": "0",
3625+
"PDISTCounter": "0,1",
3626+
"Speculative": "0"
3627+
},
34663628
{
34673629
"EventCode": "0xc4",
34683630
"UMask": "0x30",
@@ -3490,6 +3652,114 @@
34903652
"PDISTCounter": "0,1",
34913653
"Speculative": "0"
34923654
},
3655+
{
3656+
"EventCode": "0xc4",
3657+
"UMask": "0x50",
3658+
"UMaskExt": "0x00",
3659+
"EventName": "BR_INST_RETIRED.ALL_NEAR_IND",
3660+
"BriefDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT]",
3661+
"PublicDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT]",
3662+
"Counter": "0,1,2,3,4,5,6,7",
3663+
"PEBScounters": "0,1,2,3,4,5,6,7",
3664+
"SampleAfterValue": "1000003",
3665+
"MSRIndex": "0x00",
3666+
"MSRValue": "0x00",
3667+
"Precise": "1",
3668+
"CollectPEBSRecord": "2",
3669+
"TakenAlone": "0",
3670+
"CounterMask": "0",
3671+
"Invert": "0",
3672+
"EdgeDetect": "0",
3673+
"Data_LA": "0",
3674+
"L1_Hit_Indication": "0",
3675+
"Errata": "null",
3676+
"Offcore": "0",
3677+
"Deprecated": "1",
3678+
"Equal": "0",
3679+
"PDISTCounter": "0,1",
3680+
"Speculative": "0"
3681+
},
3682+
{
3683+
"EventCode": "0xc4",
3684+
"UMask": "0x50",
3685+
"UMaskExt": "0x00",
3686+
"EventName": "BR_INST_RETIRED.NEAR_INDIRECT",
3687+
"BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired. [This event is alias to BR_INST_RETIRED.ALL_NEAR_IND]",
3688+
"PublicDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired. [This event is alias to BR_INST_RETIRED.ALL_NEAR_IND]",
3689+
"Counter": "0,1,2,3,4,5,6,7",
3690+
"PEBScounters": "0,1,2,3,4,5,6,7",
3691+
"SampleAfterValue": "1000003",
3692+
"MSRIndex": "0x00",
3693+
"MSRValue": "0x00",
3694+
"Precise": "1",
3695+
"CollectPEBSRecord": "2",
3696+
"TakenAlone": "0",
3697+
"CounterMask": "0",
3698+
"Invert": "0",
3699+
"EdgeDetect": "0",
3700+
"Data_LA": "0",
3701+
"L1_Hit_Indication": "0",
3702+
"Errata": "null",
3703+
"Offcore": "0",
3704+
"Deprecated": "0",
3705+
"Equal": "0",
3706+
"PDISTCounter": "0,1",
3707+
"Speculative": "0"
3708+
},
3709+
{
3710+
"EventCode": "0xc4",
3711+
"UMask": "0x58",
3712+
"UMaskExt": "0x00",
3713+
"EventName": "BR_INST_RETIRED.ALL_NEAR_IND_OR_RET",
3714+
"BriefDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_OR_RETURN]",
3715+
"PublicDescription": "This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_OR_RETURN]",
3716+
"Counter": "0,1,2,3,4,5,6,7",
3717+
"PEBScounters": "0,1,2,3,4,5,6,7",
3718+
"SampleAfterValue": "1000003",
3719+
"MSRIndex": "0x00",
3720+
"MSRValue": "0x00",
3721+
"Precise": "1",
3722+
"CollectPEBSRecord": "2",
3723+
"TakenAlone": "0",
3724+
"CounterMask": "0",
3725+
"Invert": "0",
3726+
"EdgeDetect": "0",
3727+
"Data_LA": "0",
3728+
"L1_Hit_Indication": "0",
3729+
"Errata": "null",
3730+
"Offcore": "0",
3731+
"Deprecated": "1",
3732+
"Equal": "0",
3733+
"PDISTCounter": "0,1",
3734+
"Speculative": "0"
3735+
},
3736+
{
3737+
"EventCode": "0xc4",
3738+
"UMask": "0x58",
3739+
"UMaskExt": "0x00",
3740+
"EventName": "BR_INST_RETIRED.NEAR_INDIRECT_OR_RETURN",
3741+
"BriefDescription": "Counts the number of near indirect JMP, near indirect CALL, and RET branch instructions retired. [This event is alias to BR_INST_RETIRED.ALL_NEAR_IND_OR_RET]",
3742+
"PublicDescription": "Counts the number of near indirect JMP, near indirect CALL, and RET branch instructions retired. [This event is alias to BR_INST_RETIRED.ALL_NEAR_IND_OR_RET]",
3743+
"Counter": "0,1,2,3,4,5,6,7",
3744+
"PEBScounters": "0,1,2,3,4,5,6,7",
3745+
"SampleAfterValue": "1000003",
3746+
"MSRIndex": "0x00",
3747+
"MSRValue": "0x00",
3748+
"Precise": "1",
3749+
"CollectPEBSRecord": "2",
3750+
"TakenAlone": "0",
3751+
"CounterMask": "0",
3752+
"Invert": "0",
3753+
"EdgeDetect": "0",
3754+
"Data_LA": "0",
3755+
"L1_Hit_Indication": "0",
3756+
"Errata": "null",
3757+
"Offcore": "0",
3758+
"Deprecated": "0",
3759+
"Equal": "0",
3760+
"PDISTCounter": "0,1",
3761+
"Speculative": "0"
3762+
},
34933763
{
34943764
"EventCode": "0xc4",
34953765
"UMask": "0xfb",
@@ -4224,8 +4494,8 @@
42244494
"UMask": "0x05",
42254495
"UMaskExt": "0x00",
42264496
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024",
4227-
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
4228-
"PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
4497+
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024.",
4498+
"PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024.",
42294499
"Counter": "0,1,2,3,4,5,6,7",
42304500
"PEBScounters": "0,1,2,3,4,5,6,7",
42314501
"SampleAfterValue": "1000003",
@@ -4305,8 +4575,8 @@
43054575
"UMask": "0x05",
43064576
"UMaskExt": "0x00",
43074577
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048",
4308-
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
4309-
"PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
4578+
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048.",
4579+
"PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048.",
43104580
"Counter": "0,1,2,3,4,5,6,7",
43114581
"PEBScounters": "0,1,2,3,4,5,6,7",
43124582
"SampleAfterValue": "1000003",

‎PTL/events/pantherlake_uncore.json‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
{
22
"Header": {
3-
"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
4-
"Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.03",
5-
"DatePublished": "11/14/2025",
6-
"Version": "1.03",
3+
"Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
4+
"Info": "Performance Monitoring Events for Intel(R) Core(TM) Ultra series 3 processors (codenamed Panther Lake) - V1.04",
5+
"DatePublished": "01/23/2026",
6+
"Version": "1.04",
77
"Legend": ""
88
},
99
"Events": [

‎mapfile.csv‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -234,7 +234,7 @@ GenuineIntel-6-C6,V1.16,/ARL/events/arrowlake_lioncove_core.json,hybridcore,0x40
234234
GenuineIntel-6-C6,V1.16,/ARL/events/arrowlake_uncore.json,uncore,,,
235235
GenuineIntel-6-C6,V1.16,/ARL/events/arrowlake_uncore_experimental.json,uncore experimental,,,
236236
GenuineIntel-6-C6,V1.1,/ARL/metrics/arrowlake_metrics_lioncove_core.json,metrics,0x40,0x000003,Core
237-
GenuineIntel-6-CC,V1.03,/PTL/events/pantherlake_darkmont_core.json,hybridcore,0x20,0x000004,Atom
238-
GenuineIntel-6-CC,V1.03,/PTL/events/pantherlake_cougarcove_core.json,hybridcore,0x40,0x000004,Core
239-
GenuineIntel-6-CC,V1.03,/PTL/events/pantherlake_uncore.json,uncore,,,
237+
GenuineIntel-6-CC,V1.04,/PTL/events/pantherlake_darkmont_core.json,hybridcore,0x20,0x000004,Atom
238+
GenuineIntel-6-CC,V1.04,/PTL/events/pantherlake_cougarcove_core.json,hybridcore,0x40,0x000004,Core
239+
GenuineIntel-6-CC,V1.04,/PTL/events/pantherlake_uncore.json,uncore,,,
240240
GenuineIntel-6-DD,V1.00,/CWF/events/clearwaterforest_core.json,core,,,

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