Preserve forced-SIMD hint bits in SIMDInfo

Two SIMDInfo bits are set once during input translation, not per codegen
attempt. ClearSIMDInfo zeroed a whole slot, so a recompiled shader lost
them and the output no longer showed why a SIMD width had been forced.
Preserve them across a clear; only per-attempt bits are dropped. Also
add helpers for recording a forced SIMD width.

Author: iwwu

IGC/Compiler/CodeGenPublic.h

@@ -438,6 +438,11 @@ enum SIMDInfoBit {
                        // fits in m_SIMDInfo ***
 };
 
+// SIMDInfo bits describing a hint about the shader itself, not the outcome of one
+// codegen attempt. Set only in the input translation stage, which is not re-run
+// on a retry, so ClearSIMDInfo must preserve them.
+constexpr uint32_t g_cStickySIMDInfoBits = (1U << SIMD_FORCE_CONTENT) | (1U << SIMD_FORCE_HINT);
+
 struct SKernelProgram {
   SProgramOutput simd1;
   SProgramOutput simd8;
@@ -1191,17 +1196,19 @@ class CodeGenContext {
   void ModifySIMDInfo(SIMDMode simd, ShaderDispatchMode mode, Action action, SIMDInfoBit bit = SIMD_INFO_RESERVED) {
     uint32_t bit_value = 1UL << bit;
     bool clear = action == Action::Clear ? true : false;
+    // Clear drops the per-attempt bits only: see g_cStickySIMDInfoBits.
+    auto apply = [&](uint32_t current) { return clear ? (current & g_cStickySIMDInfoBits) : (current | bit_value); };
     switch (mode) {
     case ShaderDispatchMode::NOT_APPLICABLE:
       switch (simd) {
       case SIMDMode::SIMD8:
-        m_SIMDInfo.simd8 = clear ? 0 : m_SIMDInfo.simd8 | bit_value;
+        m_SIMDInfo.simd8 = apply(m_SIMDInfo.simd8);
         break;
       case SIMDMode::SIMD16:
-        m_SIMDInfo.simd16 = clear ? 0 : m_SIMDInfo.simd16 | bit_value;
+        m_SIMDInfo.simd16 = apply(m_SIMDInfo.simd16);
         break;
       case SIMDMode::SIMD32:
-        m_SIMDInfo.simd32 = clear ? 0 : m_SIMDInfo.simd32 | bit_value;
+        m_SIMDInfo.simd32 = apply(m_SIMDInfo.simd32);
         break;
       default:
         IGC_ASSERT_MESSAGE(0, "Unknown SIMD Mode");
@@ -1210,10 +1217,10 @@ class CodeGenContext {
       break;
 
     case ShaderDispatchMode::DUAL_SIMD8:
-      m_SIMDInfo.dual_simd8 = clear ? 0 : m_SIMDInfo.dual_simd8 | bit_value;
+      m_SIMDInfo.dual_simd8 = apply(m_SIMDInfo.dual_simd8);
       break;
     case ShaderDispatchMode::QUAD_SIMD8_DYNAMIC:
-      m_SIMDInfo.quad_simd8_dynamic = clear ? 0 : m_SIMDInfo.quad_simd8_dynamic | bit_value;
+      m_SIMDInfo.quad_simd8_dynamic = apply(m_SIMDInfo.quad_simd8_dynamic);
       break;
 
     default:
@@ -1227,6 +1234,26 @@ class CodeGenContext {
     ModifySIMDInfo(simd, mode, Action::Set, bit);
   }
 
+  // Record a hint-forced wave size. Convert lanes to SIMDMode type
+  void SetForcedWaveSizeSIMDInfo(unsigned waveSizeInLanes) {
+    if (waveSizeInLanes == 8 || waveSizeInLanes == 16 || waveSizeInLanes == 32) {
+      SetSIMDInfo(SIMD_FORCE_HINT, lanesToSIMDMode(waveSizeInLanes), ShaderDispatchMode::NOT_APPLICABLE);
+    }
+  }
+
+  // Record a hint-forced wave size for PS.
+  void SetForcedPSSIMDModeSIMDInfo(unsigned psSIMDModeMask) {
+    if (psSIMDModeMask & FLAG_PS_SIMD_MODE_FORCE_SIMD8) {
+      SetSIMDInfo(SIMD_FORCE_HINT, SIMDMode::SIMD8, ShaderDispatchMode::NOT_APPLICABLE);
+    }
+    if (psSIMDModeMask & FLAG_PS_SIMD_MODE_FORCE_SIMD16) {
+      SetSIMDInfo(SIMD_FORCE_HINT, SIMDMode::SIMD16, ShaderDispatchMode::NOT_APPLICABLE);
+    }
+    if (psSIMDModeMask & FLAG_PS_SIMD_MODE_FORCE_SIMD32) {
+      SetSIMDInfo(SIMD_FORCE_HINT, SIMDMode::SIMD32, ShaderDispatchMode::NOT_APPLICABLE);
+    }
+  }
+
   void ClearSIMDInfo(SIMDMode simd, ShaderDispatchMode mode) { ModifySIMDInfo(simd, mode, Action::Clear); }
 
   SIMDInfoStruct GetSIMDInfo() const { return m_SIMDInfo; }