Expand RISC-V vector backend with missing intrinsics

[rajeshgangam]

Summary

The RISC-V codegen backend (src/CodeGen_RISCV.cpp) currently supports only 5 operations (12 intrinsic table entries): halving_add, rounding_halving_add, widening_add, widening_sub, and widening_mul. By comparison, the ARM backend supports ~40 operation categories.

Several commonly-used operations have direct RVV instruction equivalents but are not yet mapped:

Same-width operations:

• saturating_add → vsadd.vv / vsaddu.vv
• saturating_sub → vssub.vv / vssubu.vv
• halving_sub → vasub.vv / vasubu.vv

Narrowing operations (requires infrastructure extension):

• shift_right_narrow → vnsrl / vnsra
• Saturating narrow → vnclip / vnclipu

Floating-point (noted as TODO at line 247):

• Basic float ops → vfadd, vfsub, vfmul, vfdiv, etc.

The simd_op_check_riscv.cpp test file also has minimal coverage (26 checks vs ARM's ~596).

Proposal

I'd like to incrementally add these missing intrinsics, starting with saturating add/sub which fit the existing RISCVIntrinsic table pattern with zero infrastructure changes. Each PR will be small (<100 lines) and include corresponding simd_op_check_riscv test updates.

Related issues: #7122 (simd_op_check expansion needed), #8603 (RVV feature discussion)