Add __{l,st}s{w,d}{i,x}

Fix upper 32-bit being picked from 64-bit variables
Minor optimizations

Author: Extrems

include/ogc/machine/processor.h

@@ -82,27 +82,51 @@
 
 #define __lhbrx(base,index)			\
 ({	register u16 res;				\
-	__asm__ __volatile__ ("lhbrx	%0,%1,%2" : "=r"(res) : "b%"(index), "r"(base) : "memory"); \
+	__asm__ __volatile__ ("lhbrx	%0,%1,%2" : "=r"(res) : "Ob"(index), "r"(base) : "memory"); \
 	res; })
 
 #define __lwbrx(base,index)			\
 ({	register u32 res;				\
-	__asm__ __volatile__ ("lwbrx	%0,%1,%2" : "=r"(res) : "b%"(index), "r"(base) : "memory"); \
+	__asm__ __volatile__ ("lwbrx	%0,%1,%2" : "=r"(res) : "Ob"(index), "r"(base) : "memory"); \
+	res; })
+
+#define __lswi(base,bytes)			\
+({	register u32 res;				\
+	__asm__ __volatile__ ("lswi		%0,%P1,%2" : "=&b"(res) : "Q"(*(u32*)(base)), "i"(bytes)); \
+	res; })
+
+#define __lsdi(base,bytes)			\
+({	register u64 res;				\
+	__asm__ __volatile__ ("lswi		%0,%P1,%2" : "=&b"(res) : "Q"(*(u64*)(base)), "i"(bytes)); \
 	res; })
 
 #define __lswx(base,bytes)			\
 ({	register u32 res;				\
 	__asm__ __volatile__ ("mtxer %2; lswx %0,%y1" : "=&b"(res) : "Z"(*(u32*)(base)), "r"(bytes) : "xer"); \
 	res; })
 
+#define __lsdx(base,bytes)			\
+({	register u64 res;				\
+	__asm__ __volatile__ ("mtxer %2; lswx %0,%y1" : "=&b"(res) : "Z"(*(u64*)(base)), "r"(bytes) : "xer"); \
+	res; })
+
 #define __sthbrx(base,index,value)	\
-	__asm__ __volatile__ ("sthbrx	%0,%1,%2" : : "r"(value), "b%"(index), "r"(base) : "memory")
+	__asm__ __volatile__ ("sthbrx	%0,%1,%2" : : "r"((u16)(value)), "Ob"(index), "r"(base) : "memory")
 
 #define __stwbrx(base,index,value)	\
-	__asm__ __volatile__ ("stwbrx	%0,%1,%2" : : "r"(value), "b%"(index), "r"(base) : "memory")
+	__asm__ __volatile__ ("stwbrx	%0,%1,%2" : : "r"((u32)(value)), "Ob"(index), "r"(base) : "memory")
+
+#define __stswi(base,bytes,value)	\
+	__asm__ __volatile__ ("stswi	%1,%P0,%2" : "=Q"(*(u32*)(base)) : "r"((u32)(value)), "i"(bytes));
+
+#define __stsdi(base,bytes,value)	\
+	__asm__ __volatile__ ("stswi	%1,%P0,%2" : "=Q"(*(u64*)(base)) : "r"((u64)(value)), "i"(bytes));
 
 #define __stswx(base,bytes,value)	\
-	__asm__ __volatile__ ("mtxer %2; stswx %1,%y0" : "=Z"(*(u32*)(base)) : "r"(value), "r"(bytes) : "xer");
+	__asm__ __volatile__ ("mtxer %2; stswx %1,%y0" : "=Z"(*(u32*)(base)) : "r"((u32)(value)), "r"(bytes) : "xer");
+
+#define __stsdx(base,bytes,value)	\
+	__asm__ __volatile__ ("mtxer %2; stswx %1,%y0" : "=Z"(*(u64*)(base)) : "r"((u64)(value)), "r"(bytes) : "xer");
 
 #define _CPU_MSR_GET( _msr_value ) \
   do { \

libogc/n64.c

@@ -28,6 +28,7 @@ distribution.
 #include <gctypes.h>
 #include <ogc/irq.h>
 #include <ogc/lwp.h>
+#include <ogc/machine/processor.h>
 #include <ogc/n64.h>
 #include <ogc/si.h>
 #include <ogc/system.h>
@@ -169,10 +170,13 @@ static void ShortCommandProc(s32 chan, s32 result)
 	N64ControlBlock *cb = &__N64[chan];
 
 	if (result == N64_ERR_READY) {
-		if (cb->in[0] != 0x05 || cb->in[1] != 0x00)
+		u32 type = __lswi(cb->in, 2);
+		u8 status = cb->in[2];
+
+		if (type != SI_N64_CONTROLLER)
 			cb->result = N64_ERR_NO_CONTROLLER;
 		else if (cb->status)
-			*cb->status = cb->in[2];
+			*cb->status = status;
 	}
 }
 
@@ -222,7 +226,7 @@ static void ReadProc(s32 chan, s32 result)
 	N64Status *status = (N64Status *)cb->ptr;
 
 	if (result == N64_ERR_READY) {
-		status->button = cb->in[1] << 8 | cb->in[0];
+		status->button = __lhbrx(cb->in, 0);
 		status->stickX = cb->in[2];
 		status->stickY = cb->in[3];
 	}