esp32_s2: Fixes RTCWDT protect address

Author: gerekon

src/target/esp32_s2.c

@@ -57,18 +57,18 @@
 #define ESP32_S2_TIMG1WDT_PROTECT     (ESP32_S2_TIMG1_BASE + ESP32_S2_TIMGWDT_PROTECT_OFF)
 #define ESP32_S2_RTCCNTL_BASE         0x3f408000
 #define ESP32_S2_RTCWDT_CFG_OFF       0x94
-#define ESP32_S2_RTCWDT_PROTECT_OFF   0xA8
+#define ESP32_S2_RTCWDT_PROTECT_OFF   0xAC
 #define ESP32_S2_RTCWDT_CFG           (ESP32_S2_RTCCNTL_BASE + ESP32_S2_RTCWDT_CFG_OFF)
 #define ESP32_S2_RTCWDT_PROTECT       (ESP32_S2_RTCCNTL_BASE + ESP32_S2_RTCWDT_PROTECT_OFF)
 
-#define ESP32_S2_TRACEMEM_BLOCK_SZ    	0x4000
+#define ESP32_S2_TRACEMEM_BLOCK_SZ      0x4000
 
-#define ESP32_S2_DR_REG_UART_BASE     	0x3f400000
-#define ESP32_S2_REG_UART_BASE( i )		(ESP32_S2_DR_REG_UART_BASE + (i) * 0x10000 )
-#define ESP32_S2_UART_DATE_REG(i)    	(ESP32_S2_REG_UART_BASE(i) + 0x74)
-#define ESP32_S2_CHIP_REV_REG			ESP32_S2_UART_DATE_REG(0)
-#define ESP32_S2_CHIP_REV_VAL			0x19031400
-#define ESP32_S2BETA_CHIP_REV_VAL		0x18082800
+#define ESP32_S2_DR_REG_UART_BASE       0x3f400000
+#define ESP32_S2_REG_UART_BASE(i)             (ESP32_S2_DR_REG_UART_BASE + (i) * 0x10000 )
+#define ESP32_S2_UART_DATE_REG(i)       (ESP32_S2_REG_UART_BASE(i) + 0x74)
+#define ESP32_S2_CHIP_REV_REG                   ESP32_S2_UART_DATE_REG(0)
+#define ESP32_S2_CHIP_REV_VAL                   0x19031400
+#define ESP32_S2BETA_CHIP_REV_VAL               0x18082800
 
 
 static const struct xtensa_config esp32_s2_xtensa_cfg = {
@@ -246,16 +246,16 @@ static int esp32_s2_soc_reset(struct target *target)
 	*/
 	const uint32_t esp32_reset_stub_code[] = {
 		0x00001B06,
-		0x00001106, 0x3F408038, 0x3F4080C0, 0x3F4080C4,
-		0x3F408074, 0x01583218, 0x9C492000, 0x3F408000,
-		0x50D83AA1, 0x3F4080A8, 0x3F41F064, 0x3F420064,
-		0x3F408094, 0x3F41F048, 0x3F420048, 0x3F4C10E0,
-		0x3F408038, 0x00003000, 0x41305550, 0x0459FFEE,
-		0x59FFEE41, 0xFFED4104, 0xED410459, 0xFFED31FF,
-		0xED310439, 0xFFED41FF, 0x00000439, 0x31305550,
-		0xEC41FFEC, 0x410439FF, 0x0439FFEC, 0x39FFEC41,
-		0xFFEB4104, 0xEB410459, 0x410459FF, 0x0459FFEB,
-		0x59FFEB41, 0xFFEA4104, 0x39FFEB31, 0x00700004,
+		0x00001106,0x3F408038, 0x3F4080C0,0x3F4080C4,
+		0x3F408074,0x01583218, 0x9C492000,0x3F408000,
+		0x50D83AA1,0x3F4080AC, 0x3F41F064,0x3F420064,
+		0x3F408094,0x3F41F048, 0x3F420048,0x3F4C10E0,
+		0x3F408038,0x00003000, 0x41305550,0x0459FFEE,
+		0x59FFEE41,0xFFED4104, 0xED410459,0xFFED31FF,
+		0xED310439,0xFFED41FF, 0x00000439,0x31305550,
+		0xEC41FFEC,0x410439FF, 0x0439FFEC,0x39FFEC41,
+		0xFFEB4104,0xEB410459, 0x410459FF,0x0459FFEB,
+		0x59FFEB41,0xFFEA4104, 0x39FFEB31,0x00700004,
 		0x00FFFE46
 	};
 

src/target/esp32_s2.h

@@ -41,8 +41,8 @@ enum esp32_s2_rev {
 };
 
 struct esp32_s2_common {
-	struct esp_xtensa_common 	esp_xtensa;
-	enum esp32_s2_rev			chip_rev;
+	struct esp_xtensa_common esp_xtensa;
+	enum esp32_s2_rev chip_rev;
 };
 
 static inline struct esp32_s2_common *target_to_esp32_s2(struct target *target)

src/target/esp32s2_cpu_reset_handler.S

@@ -31,7 +31,7 @@
 #define TIMG1_WDTWPROTECT_REG       0x3F420064
 #define TIMG1_WDTCONFIG0_REG        0x3F420048
 #define RTC_CNTL_WDTCONFIG0_REG     0x3F408094
-#define RTC_CNTL_WDTWPROTECT_REG    0x3F4080a8
+#define RTC_CNTL_WDTWPROTECT_REG    0x3F4080ac
 #define RTC_CNTL_OPTIONS0_REG       0x3F408000
 #define RTC_CNTL_OPTIONS0_DEF       0x1C492000
 #define RTC_CNTL_SW_SYS_RST         0x80000000