Import cleanups.

Author: Paebbels

pyEDAA/OutputFilter/Xilinx/OptimizeDesign.py

@@ -34,8 +34,8 @@
 
 from pyTooling.Decorators  import export
 
-from pyEDAA.OutputFilter.Xilinx.Common2 import Task, Phase, SubPhase, TaskWithPhases, TaskWithSubTasks, SubTask, \
-	PhaseWithChildren
+from pyEDAA.OutputFilter.Xilinx.Common2 import Task, TaskWithPhases, TaskWithSubTasks, SubTask
+from pyEDAA.OutputFilter.Xilinx.Common2 import Phase, SubPhase, PhaseWithChildren
 from pyEDAA.OutputFilter.Xilinx.Common2 import MAJOR, MAJOR_MINOR
 
 
@@ -47,9 +47,9 @@ class Phase_Retarget(Phase):
 	Used by task :class:`LogicOptimizationTask`.
 	"""
 	_START:  ClassVar[Pattern] = compile(f"^Phase {MAJOR} Retarget")
-	_FINISH: ClassVar[str]     = "Phase {phaseIndex} Retarget | Checksum:"
-	_TIME:   ClassVar[str]     = "Time (s):"
-	_FINAL:  ClassVar[str] = "Retarget | Checksum:"
+	_FINISH: ClassVar[str] =     "Phase {phaseIndex} Retarget | Checksum:"
+	_TIME:   ClassVar[str] =     "Time (s):"
+	_FINAL:  ClassVar[str] =     "Retarget | Checksum:"
 
 
 @export

pyEDAA/OutputFilter/Xilinx/PhysicalOptimizeDesign.py

@@ -30,7 +30,7 @@
 #
 """A filtering anc classification processor for AMD/Xilinx Vivado Synthesis outputs."""
 from re     import compile, Pattern
-from typing import ClassVar, Type, Tuple, Dict
+from typing import ClassVar, Type, Tuple
 
 from pyTooling.Decorators import export
 

pyEDAA/OutputFilter/Xilinx/PlaceDesign.py

@@ -30,13 +30,13 @@
 #
 """A filtering anc classification processor for AMD/Xilinx Vivado Synthesis outputs."""
 from re     import compile, Pattern
-from typing import Generator, ClassVar, List, Type, Dict, Tuple
+from typing import ClassVar, Type, Tuple
 
 from pyTooling.Decorators import export
 
-from pyEDAA.OutputFilter.Xilinx         import Line, VivadoMessage, LineKind
-from pyEDAA.OutputFilter.Xilinx.Common2 import TaskWithPhases, Phase, SubPhase, SubSubPhase, SubSubSubPhase, \
-	PhaseWithChildren, SubPhaseWithChildren, SubSubPhaseWithChildren
+from pyEDAA.OutputFilter.Xilinx.Common2 import TaskWithPhases
+from pyEDAA.OutputFilter.Xilinx.Common2 import Phase, SubPhase, SubSubPhase, SubSubSubPhase
+from pyEDAA.OutputFilter.Xilinx.Common2 import PhaseWithChildren, SubPhaseWithChildren, SubSubPhaseWithChildren
 from pyEDAA.OutputFilter.Xilinx.Common2 import MAJOR, MAJOR_MINOR, MAJOR_MINOR_MICRO, MAJOR_MINOR_MICRO_NANO
 
 

pyEDAA/OutputFilter/Xilinx/RouteDesign.py

@@ -30,14 +30,11 @@
 #
 """A filtering anc classification processor for AMD/Xilinx Vivado Synthesis outputs."""
 from re     import compile, Pattern
-from typing import Generator, ClassVar, List, Type, Dict, Tuple
+from typing import ClassVar, Type, Tuple
 
 from pyTooling.Decorators import export
-from pyTooling.Warning    import WarningCollector
 
-from pyEDAA.OutputFilter.Xilinx             import Line, VivadoMessage, LineKind
-from pyEDAA.OutputFilter.Xilinx.Common2 import TaskWithPhases, Phase, SubPhase, UnknownSubPhase, PhaseWithChildren, \
-	SubPhaseWithChildren
+from pyEDAA.OutputFilter.Xilinx.Common2     import TaskWithPhases, Phase, SubPhase, PhaseWithChildren, SubPhaseWithChildren
 from pyEDAA.OutputFilter.Xilinx.Common2     import MAJOR, MAJOR_MINOR, MAJOR_MINOR_MICRO
 from pyEDAA.OutputFilter.Xilinx.PlaceDesign import SubSubPhase
 

pyEDAA/OutputFilter/Xilinx/SynthesizeDesign.py

@@ -35,8 +35,7 @@
 from pyTooling.Decorators  import export, readonly
 from pyTooling.MetaClasses import ExtendedType, abstractmethod
 
-from pyEDAA.OutputFilter.Xilinx.Common import VHDLAssertionMessage, Line, LineKind, VivadoInfoMessage, \
-	VHDLReportMessage, VivadoMessage, VivadoWarningMessage, VivadoCriticalWarningMessage, VivadoErrorMessage
+from pyEDAA.OutputFilter.Xilinx.Common  import VHDLAssertionMessage, Line, LineKind, VivadoInfoMessage, VHDLReportMessage, VivadoMessage
 from pyEDAA.OutputFilter.Xilinx.Common2 import BaseParser
 
 TIME_MEMORY_PATTERN = re_compile(r"""Time \(s\): cpu = (\d{2}:\d{2}:\d{2}) ; elapsed = (\d{2}:\d{2}:\d{2}) . Memory \(MB\): peak = (\d+\.\d+) ; gain = (\d+\.\d+)""")