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Cleanup the macros in tx_port.h & comments in inc/*.S
- removed the trailing whitespaces Signed-off-by: Akif Ejaz <[email protected]>
1 parent 99ed67d commit 21256be

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9 files changed

+681
-672
lines changed

9 files changed

+681
-672
lines changed

ports/risc-v64/gnu/inc/tx_port.h

Lines changed: 14 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
11
/***************************************************************************
2-
* Copyright (c) 2024 Microsoft Corporation
3-
*
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* Copyright (c) 2024 Microsoft Corporation
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*
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* This program and the accompanying materials are made available under the
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* terms of the MIT License which is available at
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* https://opensource.org/licenses/MIT.
7-
*
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*
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* SPDX-License-Identifier: MIT
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**************************************************************************/
1010

@@ -236,8 +236,17 @@ UINT _tx_thread_interrupt_control(UIN
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237237
#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save;
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239-
#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE);
240-
#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save);
239+
#define TX_DISABLE __asm__ volatile("csrrci %0, mstatus, 8" : "=r" (interrupt_save) :: "memory");
240+
#define TX_RESTORE { \
241+
unsigned long _temp_mstatus; \
242+
__asm__ volatile( \
243+
"csrc mstatus, 8\n" \
244+
"andi %0, %1, 8\n" \
245+
"csrs mstatus, %0" \
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: "=&r" (_temp_mstatus) \
247+
: "r" (interrupt_save) \
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: "memory"); \
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}
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#else
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ports/risc-v64/gnu/src/tx_initialize_low_level.S

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
11
/***************************************************************************
2-
* Copyright (c) 2024 Microsoft Corporation
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*
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* Copyright (c) 2024 Microsoft Corporation
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*
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* This program and the accompanying materials are made available under the
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* terms of the MIT License which is available at
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* https://opensource.org/licenses/MIT.
7-
*
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*
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* SPDX-License-Identifier: MIT
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**************************************************************************/
1010

@@ -74,42 +74,42 @@ _tx_initialize_low_level:
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/* Save the system stack pointer. */
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/* _tx_thread_system_stack_ptr = sp; */
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la t0, _tx_thread_system_stack_ptr
77-
sd sp, 0(t0) /* Save system stack pointer */
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sd sp, 0(t0) // Save system stack pointer
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/* Pickup first free address. */
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/* _tx_initialize_unused_memory(__tx_free_memory_start); */
81-
la t0, __tx_free_memory_start /* Pickup first free address */
81+
la t0, __tx_free_memory_start // Pickup first free address
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la t1, _tx_initialize_unused_memory
83-
sd t0, 0(t1) /* Save unused memory address */
83+
sd t0, 0(t1) // Save unused memory address
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/* Initialize floating point control/status register if floating point is enabled. */
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#ifdef __riscv_flen
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li t0, 0
88-
csrw fcsr, t0 /* Clear FP control/status register */
88+
csrw fcsr, t0 // Clear FP control/status register
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#endif
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9191
ret
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9393
/* Timer Interrupt Handler Note:
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Platform-specific implementations must provide their own timer ISR.
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The timer interrupt handler should follow this execution flow:
96-
96+
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1. Disable interrupts (if not done by hardware exception entry)
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2. Allocate interrupt stack frame (65*8 bytes with FP, 32*8 bytes without)
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3. Save RA (x1) on the stack at offset 28*8
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4. Call _tx_thread_context_save to save thread context
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5. Call _tx_timer_interrupt to process the timer tick
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6. Call _tx_thread_context_restore to resume execution (does not return)
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Example (for CLINT timer):
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_tx_timer_interrupt_handler:
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addi sp, sp, -32*8
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sd ra, 28*8(sp)
107+
addi sp, sp, -32*8
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sd ra, 28*8(sp)
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call _tx_thread_context_save
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call _tx_timer_interrupt
111-
j _tx_thread_context_restore
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j _tx_thread_context_restore
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The port assumes Machine mode (M-mode) execution.
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For Supervisor mode (S-mode), use sstatus and SIE/SPIE instead of mstatus.
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See the RISC-V Privileged Specification for more details. */

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