demux.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:03:50 04/25/2024 
-- Design Name: 
-- Module Name:    demux - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity demux is
    Port ( d : in  STD_LOGIC;
           s : in  STD_LOGIC_VECTOR (1 downto 0);
           y : out  STD_LOGIC_VECTOR (3 downto 0));
end demux;

architecture Behavioral of demux is

begin

process (d,s)
begin

y <= "0000";

case s is
when "00" => y(0) <= d;
when "01" => y(1) <= d;
when "10" => y(2) <= d;
when others => y(3) <= d;

end case;

end process;

end Behavioral;