decoderdataflow.vhd

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-- Company: 
-- Engineer: 
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-- Create Date:    19:37:12 04/20/2024 
-- Design Name: 
-- Module Name:    decoderdataflow - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
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-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity decoderdataflow is
    Port ( i : in  STD_LOGIC_VECTOR (1 downto 0);
           d : out  STD_LOGIC_VECTOR (3 downto 0));
end decoderdataflow;

architecture Behavioral of decoderdataflow is

begin

d(0) <= not i(1) and not i(0);
d(1) <= not i(1) and i(0);
d(2) <= i(1) and not i(0);
d(3) <= i(1) and i(0);

end Behavioral;