add backwards compatibility APIs

Author: trmckay

core/src/main/scala/chisel3/BlackBox.scala

@@ -56,6 +56,12 @@ abstract class BlackBox(
   override protected final val requirements: Seq[String] = Seq.empty[String]
 ) extends BaseBlackBox {
 
+  def this(params: Map[String, Param]) =
+    this(params, Seq.empty[Layer], Seq.empty[String])
+
+  def this(params: Map[String, Param], knownLayers: Seq[Layer]) =
+    this(params, knownLayers, Seq.empty[String])
+
   // Find a Record port named "io" for purposes of stripping the prefix
   private[chisel3] lazy val _io: Option[Record] =
     this

core/src/main/scala/chisel3/experimental/ExtModule.scala

@@ -100,6 +100,15 @@ abstract class ExtModule(
   override protected final val knownLayers:  Seq[Layer] = Seq.empty[Layer],
   override protected final val requirements: Seq[String] = Seq.empty[String]
 ) extends BaseBlackBox {
+  def this(
+    params: Map[String, Param]
+  ) = this(params, knownLayers = Seq.empty[Layer], requirements = Seq.empty[String])
+
+  def this(
+    params:      Map[String, Param],
+    knownLayers: Seq[Layer]
+  ) = this(params, knownLayers, requirements = Seq.empty[String])
+
   private[chisel3] override def generateComponent(): Option[Component] = {
     require(!_closed, "Can't generate module more than once")
 

firrtl/src/main/scala/firrtl/ir/IR.scala

@@ -797,6 +797,26 @@ case class ExtModule(
 ) extends DefModule
     with UseSerializer
 
+@deprecated("All APIs in package firrtl are deprecated.", "Chisel 7.0.0")
+object ExtModule {
+  def apply(
+    info:    Info,
+    name:    String,
+    ports:   Seq[Port],
+    defname: String,
+    params:  Seq[Param],
+    layers:  Seq[String]
+  ): ExtModule = ExtModule(
+    info,
+    name,
+    ports,
+    defname,
+    params,
+    layers,
+    requirements = Seq.empty[String]
+  )
+}
+
 /** Intrinsic Module
   *
   * Used for compiler intrinsics.