Building SoC using LiteX and debuggin RiscV with OpenOcd

[snoop911]

I understand LiteX doesn't currently list the icepi-zero as a supported board, however, is it possible to modify a supported ECP5 board with the icepi-zero specifics? For example, changing the pin mapping in the python file colorlight_5a_75b.py or kosagi_fomu_pvt.py, etc?

If not, perhaps LiteX can just generate the top level verilog file(s) using the --no-compile switch
(python3 -m litex_boards.targets.colorlight_5a_75x --board=5a-75b --revision=8.0 --cpu-type=vexriscv --cpu-variant=standard+debug --uart-name=crossover --with-jtagbone --csr-csv=csr.csv --no-compile)
and the pin connections, timing constraints, etc would be done manually?

And assuming a VexRiscV SoC bitstream is successfully programmed, how could the CPU code be debugged using OpenOcd?

From what I've read, the biggest challenge seems to be OpenOcd's lack of support for the ftdi t231xq (no MPSSE). However, since the board exposes the JTAG via test-points, the 231xq could be removed/disabled in favor of an external (FT2232H) based jtag adapter. (There doesn't seem to be any drop in FTX232H chip that has the same FT231XQ footprint).

Unfortunately, I haven't seen any example of OpenOcd working with a RiscV running inside the Lattice. As an fpga/embedded software newcomer, not sure what's involved. How difficult or doable is this part?

Thanks!

[cheyao]

Hello!

Actually, I've already ported over and tested LiteX on the Icepi Zero in a custom fork (https://github.com/cheyao/linux-on-litex-vexriscv and https://github.com/cheyao/litex-boards). I just need to update it's pin definitions to the v1.3 version and I'll pr it back to the main repo. Hopefully I'll get this done by the end of the week.

It indeed seems that the FT231XQ is not supported by OpenOCD, but if you have a JTAG adapter, you can just solder a few wires onto the test points as you stated. The 231xq doesn't even need to be removed - just don't plug a cable into the uart port and in theory it should leave the pins floating :)

[snoop911]

I tried copying the icepi_zero platform/target py files, but can't seem to make it build:

~/litex-boards$ source litex-env/bin/activate
~/litex-boards$ python3 -m litex_boards.targets.icepi_zero --cpu-type=vexriscv --cpu-variant=standard+debug --uart-name=serial --csr-csv=csr.csv --build 2>&1 | tee build.log

meson /home/username/litex-boards/build/icepi_zero/software/include/../picolibc_src \
        -Dmultilib=false \
        -Dpicocrt=false \
        -Datomic-ungetc=false \
        -Dthread-local-storage=false \
        -Dio-long-long=true \
        -Dformat-default=integer \
        -Dincludedir=picolibc/riscv64-unknown-elf/include \
        -Dlibdir=picolibc/riscv64-unknown-elf/lib \
        --cross-file cross.txt
Directory already configured.
Just run your build command (e.g. ninja) and Meson will regenerate as necessary.
Run "meson setup --reconfigure" to force Meson to regenerate.
If build failures persist, run "meson setup --wipe" to rebuild from scratch
using the same options as passed when configuring the build.
ERROR: No such build data file as '/home/username/litex-boards/build/icepi_zero/software/libc/meson-private/build.dat'.
WARNING: Running the setup command as `meson [options]` instead of `meson setup [options]` is ambiguous and deprecated.
make: *** [/home/username/litex/litex/soc/software/libc/Makefile:44: __libc.a] Error 1
make: Leaving directory '/home/username/litex-boards/build/icepi_zero/software/libc'

Could you post the command you used to generate the bitstream?

[cheyao]

I've tried the command you used and it seems to generate a bitstream correctly, have you correctly installed litex following https://github.com/enjoy-digital/litex/wiki/Installation? Or tried to run meson setup --wipe as recommended?

Before I've been running ./icepi_zero.py --build --load directly to build the bitstream, but I think using this method you cannot pass additional flags easily