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Release 14.3 Map P.40xd (nt64)
Xilinx Map Application Log File for Design 'main'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx45-fgg484-2 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o main_map.ncd main.ngd main.pcf
Target Device : xc6slx45
Target Package : fgg484
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Dec 16 02:28:24 2014
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
WARNING:Timing:3159 - The DCM, variable_freq_clk_generator_inst/DCM_CLKGEN_1, has the attribute DFS_OSCILLATOR_MODE not set to
PHASE_FREQ_LOCK. No phase relationship exists between the input clock and CLKFX or CLKFX180 outputs of this DCM. Data paths between these
clock domains must be constrained using FROM/TO constraints.
WARNING:Timing:3175 - hi_in<0> does not clock data to hi_out<1>
WARNING:Timing:3225 - Timing constraint COMP "hi_out<1>" OFFSET = OUT 11.93 ns AFTER COMP "hi_in<0>" "RISING" ignored during timing analysis
WARNING:Pack:1653 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A timing
constraint summary below shows the failing constraints (preceded with an Asterisk (*)). Please use the Timing Analyzer (GUI) or TRCE
(command line) with the Mapped NCD and PCF files to identify which constraints and paths are failing because of the component delays
alone. If the failing path(s) is mapped to Xilinx components as expected, consider relaxing the constraint. If it is not mapped to
components as expected, re-evaluate your HDL and how synthesis is optimizing the path. To allow the tools to bypass this error, set the
environment variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1.
For more information about the Timing Analyzer, consult the Xilinx Timing Analyzer Reference manual; for more information on TRCE,
consult the Xilinx Command Line Tools User Guide "TRACE" chapter.
WARNING:Timing:3175 - hi_in<0> does not clock data to hi_out<1>
WARNING:Timing:3225 - Timing constraint COMP "hi_out<1>" OFFSET = OUT 11.93 ns
AFTER COMP "hi_in<0>" "RISING" ignored during timing analysis
INFO:Timing:3284 - This timing report was generated using estimated delay
information. For accurate numbers, please refer to the post Place and Route
timing report.
Number of Timing Constraints that were not applied: 3
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* TS_SYS_CLK3 = PERIOD TIMEGRP "SYS_CLK3" 1 | SETUP | -3.681ns| 87.169ns| 39| 58517
0 ns HIGH 50% | HOLD | 0.331ns| | 0| 0
----------------------------------------------------------------------------------------------------------
* TS_variable_freq_clk_generator_inst_clkou | SETUP | -2.082ns| 1316.331ns| 9| 18298
t_i = PERIOD TIMEGRP "variable_freq_clk_g | HOLD | 0.132ns| | 0| 0
enerator_inst_clkout_i" TS_SYS_CLK3 / 0.8 | | | | |
4 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
* TS_SDRAM_FIFO_inst_memc3_infrastructure_i | SETUP | -0.101ns| 38.720ns| 9| 4840
nst_clk0_bufg_in = PERIOD TIMEGRP "SDRAM_ | HOLD | 0.071ns| | 0| 0
FIFO_inst_memc3_infrastructure_inst_clk0_ | | | | |
bufg_in" TS_SYS_CLK3 / 1.5625 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
* TS_host_dcm_clk0 = PERIOD TIMEGRP "host_d | SETUP | 16.821ns| 4.009ns| 0| 0
cm_clk0" TS_okHostClk HIGH 50% | HOLD | -0.097ns| | 56| 5312
| MINPERIOD | 14.840ns| 5.990ns| 0| 0
----------------------------------------------------------------------------------------------------------
TS_SDRAM_FIFO_inst_memc3_infrastructure_i | MINPERIOD | 0.001ns| 1.599ns| 0| 0
nst_clk_2x_180 = PERIOD TIMEGRP "SDRAM_FI | | | | |
FO_inst_memc3_infrastructure_inst_clk_2x_ | | | | |
180" TS_SYS_CLK3 / 6.25 PHASE 0.8 ns HIGH | | | | |
50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_SDRAM_FIFO_inst_memc3_infrastructure_i | MINPERIOD | 0.001ns| 1.599ns| 0| 0
nst_clk_2x_0 = PERIOD TIMEGRP "SDRAM_FIFO | | | | |
_inst_memc3_infrastructure_inst_clk_2x_0" | | | | |
TS_SYS_CLK3 / 6.25 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TIMEGRP "okHostINOUT_grp" OFFSET = IN 9.8 | SETUP | 2.662ns| 7.168ns| 0| 0
3 ns VALID 9.83 ns BEFORE COMP "hi_in<0>" | HOLD | 1.193ns| | 0| 0
"RISING" | | | | |
----------------------------------------------------------------------------------------------------------
TS_SDRAM_FIFO_inst_memc3_infrastructure_i | SETUP | 4.798ns| 3.204ns| 0| 0
nst_mcb_drp_clk_bufg_in = PERIOD TIMEGRP | HOLD | 0.060ns| | 0| 0
"SDRAM_FIFO_inst_memc3_infrastructure_ins | | | | |
t_mcb_drp_clk_bufg_in" TS_SYS_CLK3 / 0.78 | | | | |
125 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_okHostClk = PERIOD TIMEGRP "okHostClk" | SETUP | 20.251ns| 0.579ns| 0| 0
20.83 ns HIGH 50% | HOLD | 0.257ns| | 0| 0
| MINLOWPULSE | 4.830ns| 16.000ns| 0| 0
----------------------------------------------------------------------------------------------------------
TIMEGRP "okHostINOUT_grp" OFFSET = OUT 11 | MAXDELAY | 7.002ns| 4.628ns| 0| 0
.63 ns AFTER COMP "hi_in<0>" "RISING" | | | | |
----------------------------------------------------------------------------------------------------------
COMP "hi_out<0>" OFFSET = OUT 11.93 ns AF | MAXDELAY | 7.952ns| 3.978ns| 0| 0
TER COMP "hi_in<0>" "RISING" | | | | |
----------------------------------------------------------------------------------------------------------
COMP "hi_in<7>" OFFSET = IN 13.33 ns VALI | SETUP | 10.548ns| 2.782ns| 0| 0
D 20.83 ns BEFORE COMP "hi_in<0>" "RISING | HOLD | 7.408ns| | 0| 0
" | | | | |
----------------------------------------------------------------------------------------------------------
COMP "hi_in<6>" OFFSET = IN 13.33 ns VALI | SETUP | 10.548ns| 2.782ns| 0| 0
D 20.83 ns BEFORE COMP "hi_in<0>" "RISING | HOLD | 7.408ns| | 0| 0
" | | | | |
----------------------------------------------------------------------------------------------------------
COMP "hi_in<5>" OFFSET = IN 13.33 ns VALI | SETUP | 10.548ns| 2.782ns| 0| 0
D 20.83 ns BEFORE COMP "hi_in<0>" "RISING | HOLD | 7.408ns| | 0| 0
" | | | | |
----------------------------------------------------------------------------------------------------------
COMP "hi_in<4>" OFFSET = IN 13.33 ns VALI | SETUP | 10.548ns| 2.782ns| 0| 0
D 20.83 ns BEFORE COMP "hi_in<0>" "RISING | HOLD | 7.408ns| | 0| 0
" | | | | |
----------------------------------------------------------------------------------------------------------
COMP "hi_in<2>" OFFSET = IN 14.13 ns VALI | SETUP | 11.716ns| 2.414ns| 0| 0
D 20.83 ns BEFORE COMP "hi_in<0>" "RISING | HOLD | 6.794ns| | 0| 0
" | | | | |
----------------------------------------------------------------------------------------------------------
COMP "hi_in<1>" OFFSET = IN 14.13 ns VALI | SETUP | 11.716ns| 2.414ns| 0| 0
D 20.83 ns BEFORE COMP "hi_in<0>" "RISING | HOLD | 6.794ns| | 0| 0
" | | | | |
----------------------------------------------------------------------------------------------------------
COMP "hi_in<3>" OFFSET = IN 14.13 ns VALI | SETUP | 11.771ns| 2.359ns| 0| 0
D 20.83 ns BEFORE COMP "hi_in<0>" "RISING | HOLD | 6.608ns| | 0| 0
" | | | | |
----------------------------------------------------------------------------------------------------------
COMP "hi_out<1>" OFFSET = OUT 11.93 ns AF | N/A | N/A| N/A| N/A| N/A
TER COMP "hi_in<0>" "RISING" | | | | |
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_okHostClk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+
| | Period | Actual Period | Timing Errors | Paths
Analyzed |
| Constraint | Requirement
|-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct |
Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+
|TS_okHostClk | 20.830ns| 16.000ns| 5.990ns| 0| 56| 3|
42956|
| TS_host_dcm_clk0 | 20.830ns| 5.990ns| N/A| 56| 0| 42956|
0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+
Derived Constraints for TS_SYS_CLK3
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+
| | Period | Actual Period | Timing Errors | Paths
Analyzed |
| Constraint | Requirement
|-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct |
Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+
|TS_SYS_CLK3 | 10.000ns| 87.169ns| 1105.718ns| 39| 18| 25369|
10923472|
| TS_SDRAM_FIFO_inst_memc3_infra| 12.800ns| 3.204ns| N/A| 0| 0| 13623|
0|
| structure_inst_mcb_drp_clk_buf| | | | | | |
|
| g_in | | | | | | |
|
| TS_SDRAM_FIFO_inst_memc3_infra| 1.600ns| 1.599ns| N/A| 0| 0| 0|
0|
| structure_inst_clk_2x_180 | | | | | | |
|
| TS_SDRAM_FIFO_inst_memc3_infra| 1.600ns| 1.599ns| N/A| 0| 0| 0|
0|
| structure_inst_clk_2x_0 | | | | | | |
|
| TS_SDRAM_FIFO_inst_memc3_infra| 6.400ns| 38.720ns| N/A| 9| 0| 4315|
0|
| structure_inst_clk0_bufg_in | | | | | | |
|
| TS_variable_freq_clk_generator| 11.905ns| 1316.331ns| N/A| 9| 0| 10905534|
0|
| _inst_clkout_i | | | | | | |
|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
----------+
4 constraints not met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 18 secs
Total CPU time at the beginning of Placer: 18 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:e11ba607) REAL time: 20 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:e11ba607) REAL time: 21 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:776b4f47) REAL time: 21 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:a16c678a) REAL time: 43 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:a16c678a) REAL time: 43 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:a16c678a) REAL time: 43 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:a16c678a) REAL time: 43 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:a16c678a) REAL time: 43 secs
Phase 9.8 Global Placement
..................
.........................
...........................................................................
.............................................................................................................................
......................
Phase 9.8 Global Placement (Checksum:3653dbca) REAL time: 1 mins 56 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:3653dbca) REAL time: 1 mins 57 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:ef77f5dd) REAL time: 2 mins 12 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:ef77f5dd) REAL time: 2 mins 12 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:9192a833) REAL time: 2 mins 12 secs
Total REAL time to Placer completion: 2 mins 22 secs
Total CPU time to Placer completion: 2 mins 22 secs
Running post-placement packing...
Writing output files...
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<host/hi_dcm>.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<host/hi_dcm> and
DESKEW(5).
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<host/hi_dcm> found no
EXTERN driver in CLKFB path.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<host/hi_dcm> found
non-EXTERN block <BUFG> in CLKFB path.
Now executing Pdr_LogDcm_DeskewExtern::DoCheck for block<host/hi_dcm> found NO
extern
WARNING:PhysDesignRules:372 - Gated clock. Clock net ep46trigin<0> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ep43trigin<0> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ep43trigin<11> is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ep46trigin<5> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ep43trigin<9> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ep43trigin<13> is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ep46trigin<3> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ep43trigin<1> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ep43trigin<3> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ep43trigin<5> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net ep43trigin<7> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<host/core0/core0/a0/cb0/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1_RAMD_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<host/core0/core0/a0/cb0/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2_RAMD_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[5].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[6].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[7].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[8].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[9].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[10].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[0].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[11].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[1].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[12].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[2].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[3].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
WARNING:PhysDesignRules:1414 - Issue with pin connections and/or configuration
on
block:<SDRAM_FIFO_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_addr
_delay_obuft[4].delay_addr_inst>:<IODELAY2_IODELAY2>. When DELAY_SRC is not
IO programming the T input pin is not used and will be ignored.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 30
Slice Logic Utilization:
Number of Slice Registers: 4,670 out of 54,576 8%
Number used as Flip Flops: 4,670
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 7,446 out of 27,288 27%
Number used as logic: 7,253 out of 27,288 26%
Number using O6 output only: 6,324
Number using O5 output only: 165
Number using O5 and O6: 764
Number used as ROM: 0
Number used as Memory: 48 out of 6,408 1%
Number used as Dual Port RAM: 20
Number using O6 output only: 12
Number using O5 output only: 0
Number using O5 and O6: 8
Number used as Single Port RAM: 24
Number using O6 output only: 16
Number using O5 output only: 0
Number using O5 and O6: 8
Number used as Shift Register: 4
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 145
Number with same-slice register load: 122
Number with same-slice carry load: 23
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,647 out of 6,822 38%
Nummber of MUXCYs used: 1,432 out of 13,644 10%
Number of LUT Flip Flop pairs used: 8,686
Number with an unused Flip Flop: 4,275 out of 8,686 49%
Number with an unused LUT: 1,240 out of 8,686 14%
Number of fully used LUT-FF pairs: 3,171 out of 8,686 36%
Number of unique control sets: 188
Number of slice register sites lost
to control set restrictions: 658 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 191 out of 316 60%
Number of LOCed IOBs: 191 out of 191 100%
IOB Flip Flops: 56
IOB Master Pads: 12
IOB Slave Pads: 12
Specific Feature Utilization:
Number of RAMB16BWERs: 53 out of 116 45%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 2 out of 32 6%
Number used as BUFIO2s: 2
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 6 out of 16 37%
Number used as BUFGs: 6
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 2 out of 8 25%
Number used as DCMs: 1
Number used as DCM_CLKGENs: 1
Number of ILOGIC2/ISERDES2s: 16 out of 376 4%
Number used as ILOGIC2s: 16
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 53 out of 376 14%
Number used as IODELAY2s: 29
Number used as IODRP2s: 2
Number used as IODRP2_MCBs: 22
Number of OLOGIC2/OSERDES2s: 69 out of 376 18%
Number used as OLOGIC2s: 24
Number used as OSERDES2s: 45
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 1 out of 4 25%
Number of DSP48A1s: 8 out of 58 13%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 1 out of 2 50%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 4.47
Peak Memory Usage: 619 MB
Total REAL time to MAP completion: 2 mins 27 secs
Total CPU time to MAP completion: 2 mins 27 secs
Mapping completed.
See MAP report file "main_map.mrp" for details.