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·486 lines (420 loc) · 33 KB
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Release 14.3 par P.40xd (nt64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
JVOIGTS-OEPHYS:: Tue Dec 16 02:30:54 2014
par -w -intstyle ise -ol high -mt off main_map.ncd main.ncd main.pcf
Constraints file: main.pcf.
Loading device for application Rf_Device from file '6slx45.nph' in environment C:\Xilinx\14.3\ISE_DS\ISE\.
"main" is an NCD, version 3.2, device xc6slx45, package fgg484, speed -2
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.23 2012-10-12".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 4,670 out of 54,576 8%
Number used as Flip Flops: 4,670
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 7,446 out of 27,288 27%
Number used as logic: 7,253 out of 27,288 26%
Number using O6 output only: 6,324
Number using O5 output only: 165
Number using O5 and O6: 764
Number used as ROM: 0
Number used as Memory: 48 out of 6,408 1%
Number used as Dual Port RAM: 20
Number using O6 output only: 12
Number using O5 output only: 0
Number using O5 and O6: 8
Number used as Single Port RAM: 24
Number using O6 output only: 16
Number using O5 output only: 0
Number using O5 and O6: 8
Number used as Shift Register: 4
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 145
Number with same-slice register load: 122
Number with same-slice carry load: 23
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,647 out of 6,822 38%
Nummber of MUXCYs used: 1,432 out of 13,644 10%
Number of LUT Flip Flop pairs used: 8,686
Number with an unused Flip Flop: 4,275 out of 8,686 49%
Number with an unused LUT: 1,240 out of 8,686 14%
Number of fully used LUT-FF pairs: 3,171 out of 8,686 36%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 191 out of 316 60%
Number of LOCed IOBs: 191 out of 191 100%
IOB Flip Flops: 56
IOB Master Pads: 12
IOB Slave Pads: 12
Specific Feature Utilization:
Number of RAMB16BWERs: 53 out of 116 45%
Number of RAMB8BWERs: 0 out of 232 0%
Number of BUFIO2/BUFIO2_2CLKs: 2 out of 32 6%
Number used as BUFIO2s: 2
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 6 out of 16 37%
Number used as BUFGs: 6
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 2 out of 8 25%
Number used as DCMs: 1
Number used as DCM_CLKGENs: 1
Number of ILOGIC2/ISERDES2s: 16 out of 376 4%
Number used as ILOGIC2s: 16
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 53 out of 376 14%
Number used as IODELAY2s: 29
Number used as IODRP2s: 2
Number used as IODRP2_MCBs: 22
Number of OLOGIC2/OSERDES2s: 69 out of 376 18%
Number used as OLOGIC2s: 24
Number used as OSERDES2s: 45
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 1 out of 4 25%
Number of DSP48A1s: 8 out of 58 13%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 1 out of 2 50%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
WARNING:Timing:3159 - The DCM, variable_freq_clk_generator_inst/DCM_CLKGEN_1, has the attribute DFS_OSCILLATOR_MODE not set to
PHASE_FREQ_LOCK. No phase relationship exists between the input clock and CLKFX or CLKFX180 outputs of this DCM. Data paths between these
clock domains must be constrained using FROM/TO constraints.
WARNING:Timing:3175 - hi_in<0> does not clock data to hi_out<1>
WARNING:Timing:3225 - Timing constraint COMP "hi_out<1>" OFFSET = OUT 11.93 ns AFTER COMP "hi_in<0>" "RISING"; ignored during timing
analysis
Starting initial Timing Analysis. REAL time: 9 secs
Finished initial Timing Analysis. REAL time: 9 secs
WARNING:Par:288 - The signal host/core0/core0/a0/cb0/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route
this signal.
WARNING:Par:288 - The signal host/core0/core0/a0/cb0/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route
this signal.
Starting Router
Phase 1 : 52651 unrouted; REAL time: 10 secs
Phase 2 : 44693 unrouted; REAL time: 12 secs
Phase 3 : 20541 unrouted; REAL time: 27 secs
Phase 4 : 20556 unrouted; (Setup:736907, Hold:19147, Component Switching Limit:0) REAL time: 31 secs
Updating file: main.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:781120, Hold:19147, Component Switching Limit:0) REAL time: 56 secs
Phase 6 : 0 unrouted; (Setup:778428, Hold:19147, Component Switching Limit:0) REAL time: 1 mins
Updating file: main.ncd with current fully routed design.
Phase 7 : 0 unrouted; (Setup:778428, Hold:19147, Component Switching Limit:0) REAL time: 1 mins 23 secs
Phase 8 : 0 unrouted; (Setup:778428, Hold:19147, Component Switching Limit:0) REAL time: 1 mins 23 secs
WARNING:Route:522 - Unusually high hold time violation detected among 7 connections.The router will continue and try to fix it
SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc<8>:AQ ->
SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg<8>:AX -2386
SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc<7>:DQ ->
SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg<7>:DX -2311
SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc<7>:DMUX ->
SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg<7>:CX -2229
SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc<7>:CMUX ->
SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg<7>:AX -2227
SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc<7>:CQ ->
SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg<7>:BX -2110
SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc<7>:AQ ->
SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg<3>:BX -2083
SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc<7>:BMUX ->
SDRAM_FIFO_inst/okPipeIn_fifo/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg<3>:CX -2001
Phase 9 : 0 unrouted; (Setup:778428, Hold:0, Component Switching Limit:0) REAL time: 2 mins 18 secs
Phase 10 : 0 unrouted; (Setup:728179, Hold:0, Component Switching Limit:0) REAL time: 2 mins 19 secs
Total REAL time to Router completion: 2 mins 19 secs
Total CPU time to Router completion: 2 mins 23 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| dataclk | BUFGMUX_X2Y1| No | 718 | 0.667 | 2.375 |
+---------------------+--------------+------+------+------------+-------------+
|SDRAM_FIFO_inst/c3_m | | | | | |
| cb_drp_clk | BUFGMUX_X2Y2| No | 100 | 0.092 | 1.809 |
+---------------------+--------------+------+------+------------+-------------+
| ok1<24> | BUFGMUX_X2Y3| No | 557 | 0.704 | 2.414 |
+---------------------+--------------+------+------+------------+-------------+
|SDRAM_FIFO_inst/memc | | | | | |
|3_infrastructure_ins | | | | | |
|t/sys_clk_ibufg_BUFG | | | | | |
| | BUFGMUX_X3Y13| No | 26 | 0.056 | 1.769 |
+---------------------+--------------+------+------+------------+-------------+
|SDRAM_FIFO_inst/c3_c | | | | | |
| lk0 | BUFGMUX_X2Y4| No | 130 | 0.041 | 1.772 |
+---------------------+--------------+------+------+------------+-------------+
|DAC_output_8/state_c | | | | | |
| lk_BUFG | BUFGMUX_X2Y12| No | 64 | 0.057 | 1.768 |
+---------------------+--------------+------+------+------------+-------------+
| ep46trigin<0> | Local| | 1 | 0.000 | 0.888 |
+---------------------+--------------+------+------+------------+-------------+
| ep46trigin<2> | Local| | 1 | 0.000 | 1.063 |
+---------------------+--------------+------+------+------------+-------------+
| ep43trigin<0> | Local| | 4 | 0.475 | 2.494 |
+---------------------+--------------+------+------+------------+-------------+
| ep43trigin<2> | Local| | 4 | 0.638 | 2.801 |
+---------------------+--------------+------+------+------------+-------------+
| ep43trigin<11> | Local| | 1 | 0.000 | 1.266 |
+---------------------+--------------+------+------+------------+-------------+
| ep43trigin<12> | Local| | 1 | 0.000 | 1.698 |
+---------------------+--------------+------+------+------------+-------------+
| hi_in_0_IBUFG | Local| | 4 | 0.414 | 2.998 |
+---------------------+--------------+------+------+------------+-------------+
| ep46trigin<4> | Local| | 1 | 0.000 | 0.568 |
+---------------------+--------------+------+------+------------+-------------+
| ep46trigin<5> | Local| | 1 | 0.000 | 1.021 |
+---------------------+--------------+------+------+------------+-------------+
| ep46trigin<6> | Local| | 1 | 0.000 | 0.752 |
+---------------------+--------------+------+------+------------+-------------+
| ep46trigin<7> | Local| | 1 | 0.000 | 1.021 |
+---------------------+--------------+------+------+------------+-------------+
| ep43trigin<8> | Local| | 1 | 0.000 | 0.517 |
+---------------------+--------------+------+------+------------+-------------+
| ep43trigin<9> | Local| | 1 | 0.000 | 0.972 |
+---------------------+--------------+------+------+------------+-------------+
| ep43trigin<10> | Local| | 1 | 0.000 | 1.518 |
+---------------------+--------------+------+------+------------+-------------+
| ep43trigin<13> | Local| | 1 | 0.000 | 1.887 |
+---------------------+--------------+------+------+------------+-------------+
| ep43trigin<14> | Local| | 1 | 0.000 | 0.591 |
+---------------------+--------------+------+------+------------+-------------+
| ep43trigin<15> | Local| | 1 | 0.000 | 0.700 |
+---------------------+--------------+------+------+------------+-------------+
|SDRAM_FIFO_inst/c3_s | | | | | |
| ysclk_2x | Local| | 34 | 0.704 | 1.551 |
+---------------------+--------------+------+------+------------+-------------+
|SDRAM_FIFO_inst/c3_s | | | | | |
| ysclk_2x_180 | Local| | 37 | 0.723 | 1.570 |
+---------------------+--------------+------+------+------------+-------------+
|SDRAM_FIFO_inst/memc | | | | | |
|3_wrapper_inst/memc3 | | | | | |
|_mcb_raw_wrapper_ins | | | | | |
| t/ioi_drp_clk | Local| | 22 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|host/core0/core0/a0/ | | | | | |
| d0/div<4> | Local| | 3 | 0.000 | 4.342 |
+---------------------+--------------+------+------+------------+-------------+
|SDRAM_FIFO_inst/memc | | | | | |
|3_wrapper_inst/memc3 | | | | | |
|_mcb_raw_wrapper_ins | | | | | |
| t/idelay_dqs_ioi_s | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|SDRAM_FIFO_inst/memc | | | | | |
|3_wrapper_inst/memc3 | | | | | |
|_mcb_raw_wrapper_ins | | | | | |
| t/idelay_dqs_ioi_m | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|SDRAM_FIFO_inst/memc | | | | | |
|3_wrapper_inst/memc3 | | | | | |
|_mcb_raw_wrapper_ins | | | | | |
| t/idelay_udqs_ioi_s | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|SDRAM_FIFO_inst/memc | | | | | |
|3_wrapper_inst/memc3 | | | | | |
|_mcb_raw_wrapper_ins | | | | | |
| t/idelay_udqs_ioi_m | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
| ep44trigin<0> | Local| | 1 | 0.000 | 0.560 |
+---------------------+--------------+------+------+------------+-------------+
| ep45trigin<0> | Local| | 1 | 0.000 | 0.333 |
+---------------------+--------------+------+------+------------+-------------+
| ep45trigin<1> | Local| | 1 | 0.000 | 1.430 |
+---------------------+--------------+------+------+------------+-------------+
| ep44trigin<1> | Local| | 4 | 1.234 | 2.749 |
+---------------------+--------------+------+------+------------+-------------+
| ep46trigin<1> | Local| | 1 | 0.000 | 0.548 |
+---------------------+--------------+------+------+------------+-------------+
| ep46trigin<3> | Local| | 1 | 0.000 | 1.028 |
+---------------------+--------------+------+------+------------+-------------+
| ep43trigin<1> | Local| | 3 | 0.254 | 1.244 |
+---------------------+--------------+------+------+------------+-------------+
| ep43trigin<3> | Local| | 4 | 0.683 | 2.151 |
+---------------------+--------------+------+------+------------+-------------+
| ep43trigin<4> | Local| | 3 | 0.718 | 3.386 |
+---------------------+--------------+------+------+------------+-------------+
| ep43trigin<5> | Local| | 4 | 0.707 | 2.531 |
+---------------------+--------------+------+------+------------+-------------+
| ep43trigin<6> | Local| | 4 | 0.531 | 1.896 |
+---------------------+--------------+------+------+------------+-------------+
| ep43trigin<7> | Local| | 4 | 0.224 | 1.680 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 728179 (Setup: 728179, Hold: 0, Component Switching Limit: 0)
WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design.
Review the timing report using Timing Analyzer (In ISE select "Post-Place &
Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options
are set in the tools for timing closure.
Use the Xilinx "SmartXplorer" script to try special combinations of
options known to produce very good results.
Visit the Xilinx technical support web at http://support.xilinx.com and go to
either "Troubleshoot->Tech Tips->Timing & Constraints" or "
TechXclusives->Timing Closure" for tips and suggestions for meeting timing
in your design.
Number of Timing Constraints that were not applied: 3
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* TS_SYS_CLK3 = PERIOD TIMEGRP "SYS_CLK3" 1 | SETUP | -19.092ns| 410.251ns| 40| 546047
0 ns HIGH 50% | HOLD | 0.458ns| | 0| 0
----------------------------------------------------------------------------------------------------------
* TS_SDRAM_FIFO_inst_memc3_infrastructure_i | SETUP | -10.947ns| 3509.440ns| 9| 96599
nst_clk0_bufg_in = PERIOD TIMEGRP | HOLD | 0.271ns| | 0| 0
"SDRAM_FIFO_inst_memc3_infrastructure_in | | | | |
st_clk0_bufg_in" TS_SYS_CLK3 / 1. | | | | |
5625 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
* TS_variable_freq_clk_generator_inst_clkou | SETUP | -4.417ns| 16.321ns| 117| 85533
t_i = PERIOD TIMEGRP "variable_fr | HOLD | 0.385ns| | 0| 0
eq_clk_generator_inst_clkout_i" TS_SYS_CL | | | | |
K3 / 0.84 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_SDRAM_FIFO_inst_memc3_infrastructure_i | MINPERIOD | 0.001ns| 1.599ns| 0| 0
nst_clk_2x_180 = PERIOD TIMEGRP " | | | | |
SDRAM_FIFO_inst_memc3_infrastructure_inst | | | | |
_clk_2x_180" TS_SYS_CLK3 / 6.25 P | | | | |
HASE 0.8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_SDRAM_FIFO_inst_memc3_infrastructure_i | MINPERIOD | 0.001ns| 1.599ns| 0| 0
nst_clk_2x_0 = PERIOD TIMEGRP "SD | | | | |
RAM_FIFO_inst_memc3_infrastructure_inst_c | | | | |
lk_2x_0" TS_SYS_CLK3 / 6.25 HIGH | | | | |
50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_SDRAM_FIFO_inst_memc3_infrastructure_i | SETUP | 1.670ns| 9.919ns| 0| 0
nst_mcb_drp_clk_bufg_in = PERIOD | HOLD | 0.389ns| | 0| 0
TIMEGRP "SDRAM_FIFO_inst_memc3_in | | | | |
frastructure_inst_mcb_drp_clk_bufg_in" | | | | |
TS_SYS_CLK3 / 0.78125 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
COMP "hi_in<7>" OFFSET = IN 13.33 ns VALI | SETUP | 1.740ns| 11.590ns| 0| 0
D 20.83 ns BEFORE COMP "hi_in<0>" | HOLD | 8.799ns| | 0| 0
"RISING" | | | | |
----------------------------------------------------------------------------------------------------------
COMP "hi_in<6>" OFFSET = IN 13.33 ns VALI | SETUP | 2.677ns| 10.653ns| 0| 0
D 20.83 ns BEFORE COMP "hi_in<0>" | HOLD | 9.161ns| | 0| 0
"RISING" | | | | |
----------------------------------------------------------------------------------------------------------
COMP "hi_in<5>" OFFSET = IN 13.33 ns VALI | SETUP | 2.837ns| 10.493ns| 0| 0
D 20.83 ns BEFORE COMP "hi_in<0>" | HOLD | 9.002ns| | 0| 0
"RISING" | | | | |
----------------------------------------------------------------------------------------------------------
COMP "hi_in<4>" OFFSET = IN 13.33 ns VALI | SETUP | 3.073ns| 10.257ns| 0| 0
D 20.83 ns BEFORE COMP "hi_in<0>" | HOLD | 8.829ns| | 0| 0
"RISING" | | | | |
----------------------------------------------------------------------------------------------------------
COMP "hi_out<0>" OFFSET = OUT 11.93 ns AF | MAXDELAY | 3.133ns| 8.797ns| 0| 0
TER COMP "hi_in<0>" "RISING" | | | | |
----------------------------------------------------------------------------------------------------------
TIMEGRP "okHostINOUT_grp" OFFSET = IN 9.8 | SETUP | 4.110ns| 5.720ns| 0| 0
3 ns VALID 9.83 ns BEFORE COMP "h | HOLD | 0.470ns| | 0| 0
i_in<0>" "RISING" | | | | |
----------------------------------------------------------------------------------------------------------
TS_host_dcm_clk0 = PERIOD TIMEGRP "host_d | SETUP | 4.438ns| 16.392ns| 0| 0
cm_clk0" TS_okHostClk HIGH 50% | HOLD | 0.378ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_okHostClk = PERIOD TIMEGRP "okHostClk" | SETUP | 19.213ns| 1.617ns| 0| 0
20.83 ns HIGH 50% | HOLD | 0.229ns| | 0| 0
| MINLOWPULSE | 4.830ns| 16.000ns| 0| 0
----------------------------------------------------------------------------------------------------------
TIMEGRP "okHostINOUT_grp" OFFSET = OUT 11 | MAXDELAY | 4.851ns| 6.779ns| 0| 0
.63 ns AFTER COMP "hi_in<0>" "RIS | | | | |
ING" | | | | |
----------------------------------------------------------------------------------------------------------
COMP "hi_in<1>" OFFSET = IN 14.13 ns VALI | SETUP | 6.868ns| 7.262ns| 0| 0
D 20.83 ns BEFORE COMP "hi_in<0>" | HOLD | 8.867ns| | 0| 0
"RISING" | | | | |
----------------------------------------------------------------------------------------------------------
COMP "hi_in<2>" OFFSET = IN 14.13 ns VALI | SETUP | 8.086ns| 6.044ns| 0| 0
D 20.83 ns BEFORE COMP "hi_in<0>" | HOLD | 8.019ns| | 0| 0
"RISING" | | | | |
----------------------------------------------------------------------------------------------------------
COMP "hi_in<3>" OFFSET = IN 14.13 ns VALI | SETUP | 8.800ns| 5.330ns| 0| 0
D 20.83 ns BEFORE COMP "hi_in<0>" | HOLD | 7.897ns| | 0| 0
"RISING" | | | | |
----------------------------------------------------------------------------------------------------------
COMP "hi_out<1>" OFFSET = OUT 11.93 ns AF | N/A | N/A| N/A| N/A| N/A
TER COMP "hi_in<0>" "RISING" | | | | |
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_okHostClk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_okHostClk | 20.830ns| 16.000ns| 16.392ns| 0| 0| 3| 42956|
| TS_host_dcm_clk0 | 20.830ns| 16.392ns| N/A| 0| 0| 42956| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_SYS_CLK3
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_SYS_CLK3 | 10.000ns| 410.251ns| 5483.500ns| 40| 126| 25369| 10923472|
| TS_SDRAM_FIFO_inst_memc3_infra| 12.800ns| 9.919ns| N/A| 0| 0| 13623| 0|
| structure_inst_mcb_drp_clk_buf| | | | | | | |
| g_in | | | | | | | |
| TS_SDRAM_FIFO_inst_memc3_infra| 1.600ns| 1.599ns| N/A| 0| 0| 0| 0|
| structure_inst_clk_2x_180 | | | | | | | |
| TS_SDRAM_FIFO_inst_memc3_infra| 1.600ns| 1.599ns| N/A| 0| 0| 0| 0|
| structure_inst_clk_2x_0 | | | | | | | |
| TS_SDRAM_FIFO_inst_memc3_infra| 6.400ns| 3509.440ns| N/A| 9| 0| 4315| 0|
| structure_inst_clk0_bufg_in | | | | | | | |
| TS_variable_freq_clk_generator| 11.905ns| 16.321ns| N/A| 117| 0| 10905534| 0|
| _inst_clkout_i | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
3 constraints not met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 2 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 2 mins 21 secs
Total CPU time to PAR completion: 2 mins 25 secs
Peak Memory Usage: 620 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - 166 errors found.
Number of error messages: 0
Number of warning messages: 9
Number of info messages: 0
Writing design to file main.ncd
PAR done!