feat: Add support for the arm-qemu-stm32 platform, update related dependencies and build configurations.

Author: luodeb

Cargo.lock

@@ -69,3 +69,8 @@ axipi = { path = "modules/axipi" }
 
 [profile.release]
 lto = true
+
+[patch.crates-io]
+axplat-arm-qemu-stm32 = { path = "crates/axplat_crates/platforms/axplat-arm-qemu-stm32" }
+aarch32-cpu = { path = "crates/aarch32-cpu" }
+axcpu = { path = "crates/axcpu" }

Cargo.toml

@@ -109,7 +109,11 @@ else ifeq ($(ARCH), riscv64)
 else ifeq ($(ARCH), loongarch64)
   TARGET := loongarch64-unknown-none-softfloat
 else ifeq ($(ARCH), arm)
-  TARGET := armv7a-none-eabi
+  ifeq ($(PLAT_NAME), arm-qemu-stm32)
+    TARGET := thumbv7m-none-eabi
+  else
+    TARGET := armv7a-none-eabi
+  endif
 else
   $(error "ARCH" must be one of "x86_64", "riscv64", "aarch64", "loongarch64" or "arm")
 endif

Makefile

@@ -0,0 +1,120 @@
+OUTPUT_ARCH(arm)
+
+/* STM32F100RB: 128KB Flash at 0x08000000, 8KB SRAM at 0x20000000 */
+FLASH_BASE = 0x08000000;
+FLASH_SIZE = 0x20000;       /* 128KB */
+SRAM_BASE  = 0x20000000;
+SRAM_SIZE  = 0x2000;        /* 8KB */
+
+ENTRY(_start)
+
+MEMORY
+{
+    FLASH (RX)  : ORIGIN = FLASH_BASE, LENGTH = FLASH_SIZE
+    SRAM (RW)   : ORIGIN = SRAM_BASE,  LENGTH = SRAM_SIZE
+}
+
+SECTIONS
+{
+    . = ORIGIN(FLASH);
+    _skernel = .;
+
+    /* Vector table MUST be first — Cortex-M reads initial SP and reset vector from here */
+    .vector_table : ALIGN(4) {
+        KEEP(*(.vector_table))
+    } > FLASH
+
+    .text : ALIGN(4) {
+        _stext = .;
+        *(.text.boot)
+        *(.text .text.*)
+        . = ALIGN(4);
+        _etext = .;
+    } > FLASH
+
+    _srodata = .;
+    .rodata : ALIGN(4) {
+        *(.rodata .rodata.*)
+        *(.srodata .srodata.*)
+        *(.sdata2 .sdata2.*)
+    } > FLASH
+
+    .init_array : ALIGN(4) {
+        __init_array_start = .;
+        *(.init_array .init_array.*)
+        __init_array_end = .;
+    } > FLASH
+
+    .ARM.exidx : {
+        *(.ARM.exidx .ARM.exidx.*)
+    } > FLASH
+
+    . = ALIGN(4);
+    _erodata = .;
+
+    /* .data goes in SRAM but loaded from Flash (AT> FLASH) */
+    . = ORIGIN(SRAM);
+    _sidata = LOADADDR(.data);
+    .data : AT(_erodata) ALIGN(4) {
+        _sdata = .;
+        KEEP(*(.data.boot_page_table))
+        KEEP(*(.data .data.*))
+        KEEP(*(.sdata .sdata.*))
+        KEEP(*(.got .got.*))
+        KEEP(*(linkme_ANY))
+        KEEP(*(linkm2_ANY))
+        KEEP(*(linkme_IRQ))
+        KEEP(*(linkm2_IRQ))
+        KEEP(*(linkme_PAGE_FAULT))
+        KEEP(*(linkm2_PAGE_FAULT))
+        KEEP(*(linkme_SYSCALL))
+        KEEP(*(linkm2_SYSCALL))
+        KEEP(*(axns_resource))
+
+        . = ALIGN(64);
+        _percpu_start = .;
+        _percpu_load_start = .;
+        KEEP(*(.percpu .percpu.*))
+        _percpu_load_end = .;
+        _percpu_end = .;
+    } > SRAM
+
+    .tdata : ALIGN(4) {
+        _stdata = .;
+        *(.tdata .tdata.*)
+        _etdata = .;
+    } > SRAM AT> FLASH
+
+    .tbss : ALIGN(4) {
+        _stbss = .;
+        *(.tbss .tbss.*)
+        *(.tcommon)
+        _etbss = .;
+    } > SRAM
+
+    . = ALIGN(4);
+    _edata = .;
+
+    .bss.stack (NOLOAD) : ALIGN(8) {
+        boot_stack = .;
+        *(.bss.stack .bss.stack.*)
+        . = ALIGN(8);
+        boot_stack_top = .;
+    } > SRAM
+
+    /* BSS in SRAM (before stack, so BSS clearing won't corrupt stack frames) */
+    .bss : ALIGN(4) {
+        _sbss = .;
+        *(.bss .bss.*)
+        *(.sbss .sbss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = .;
+    } > SRAM
+
+    _ekernel = .;
+
+    /DISCARD/ : {
+        *(.comment) *(.gnu*) *(.note*) *(.eh_frame*)
+    }
+}

configs/linker_arm-qemu-stm32.lds

@@ -13,6 +13,7 @@ aarch64-phytium-pi = ["dep:axplat-aarch64-phytium-pi"]
 riscv64-qemu-virt = ["dep:axplat-riscv64-qemu-virt"]
 loongarch64-qemu-virt = ["dep:axplat-loongarch64-qemu-virt"]
 arm-qemu-virt = ["dep:axplat-arm-qemu-virt"]
+arm-qemu-stm32 = ["dep:axplat-arm-qemu-stm32"]
 
 [dependencies]
 cfg-if = "1.0"
@@ -29,9 +30,10 @@ axplat-aarch64-phytium-pi = { version = "0.4", features = ["smp", "irq"], option
 
 [target.'cfg(target_arch = "arm")'.dependencies]
 axplat-arm-qemu-virt = { version = "0.4", features = ["smp", "irq"], optional = true }
+axplat-arm-qemu-stm32 = { version = "0.1", optional = true }
 
 [target.'cfg(target_arch = "riscv64")'.dependencies]
 axplat-riscv64-qemu-virt = { version = "0.4", features = ["smp", "irq"], optional = true }
 
 [target.'cfg(target_arch = "loongarch64")'.dependencies]
-axplat-loongarch64-qemu-virt = { version = "0.4", features = ["smp", "irq"], optional = true }
+axplat-loongarch64-qemu-virt = { version = "0.4", features = ["smp", "irq"], optional = true }

examples/helloworld-myplat/Cargo.toml

@@ -18,6 +18,8 @@ cfg_if::cfg_if! {
         extern crate axplat_loongarch64_qemu_virt;
     } else if #[cfg(all(target_arch = "arm", feature = "arm-qemu-virt"))] {
         extern crate axplat_arm_qemu_virt;
+    } else if #[cfg(all(target_arch = "arm", feature = "arm-qemu-stm32"))] {
+        extern crate axplat_arm_qemu_stm32;
     } else {
         #[cfg(target_os = "none")] // ignore in rust-analyzer & cargo test
         compile_error!("No platform crate linked!\n\nPlease add `extern crate <platform>` in your code.");

examples/helloworld-myplat/src/main.rs

@@ -10,17 +10,17 @@ repository = "https://github.com/arceos-org/arceos/tree/main/modules/axhal"
 documentation = "https://arceos-org.github.io/arceos/axhal/index.html"
 
 [features]
-smp = ["axplat-x86-pc?/smp", "axplat-aarch64-qemu-virt?/smp", "axplat-riscv64-qemu-virt?/smp", "axplat-loongarch64-qemu-virt?/smp", "axplat-arm-qemu-virt?/smp", "axplat/smp"]
-irq = ["linkme", "axplat-x86-pc?/irq", "axplat-aarch64-qemu-virt?/irq", "axplat-riscv64-qemu-virt?/irq", "axplat-loongarch64-qemu-virt?/irq",  "axplat-arm-qemu-virt?/irq", "axplat/irq"]
-fp-simd = ["axcpu/fp-simd", "axplat-x86-pc?/fp-simd", "axplat-aarch64-qemu-virt?/fp-simd", "axplat-riscv64-qemu-virt?/fp-simd", "axplat-loongarch64-qemu-virt?/fp-simd", "axplat-arm-qemu-virt?/fp-simd"]
-rtc = ["axplat-x86-pc?/rtc", "axplat-aarch64-qemu-virt?/rtc", "axplat-riscv64-qemu-virt?/rtc", "axplat-loongarch64-qemu-virt?/rtc", "axplat-arm-qemu-virt?/rtc"]
+smp = ["axplat-x86-pc?/smp", "axplat-aarch64-qemu-virt?/smp", "axplat-riscv64-qemu-virt?/smp", "axplat-loongarch64-qemu-virt?/smp", "axplat-arm-qemu-virt?/smp", "axplat-arm-qemu-stm32?/smp", "axplat/smp"]
+irq = ["linkme", "axplat-x86-pc?/irq", "axplat-aarch64-qemu-virt?/irq", "axplat-riscv64-qemu-virt?/irq", "axplat-loongarch64-qemu-virt?/irq",  "axplat-arm-qemu-virt?/irq", "axplat-arm-qemu-stm32?/irq", "axplat/irq"]
+fp-simd = ["axcpu/fp-simd", "axplat-x86-pc?/fp-simd", "axplat-aarch64-qemu-virt?/fp-simd", "axplat-riscv64-qemu-virt?/fp-simd", "axplat-loongarch64-qemu-virt?/fp-simd", "axplat-arm-qemu-virt?/fp-simd", "axplat-arm-qemu-stm32?/fp-simd"]
+rtc = ["axplat-x86-pc?/rtc", "axplat-aarch64-qemu-virt?/rtc", "axplat-riscv64-qemu-virt?/rtc", "axplat-loongarch64-qemu-virt?/rtc", "axplat-arm-qemu-virt?/rtc", "axplat-arm-qemu-stm32?/rtc"]
 paging = ["axalloc", "page_table_multiarch"]
 tls = ["axcpu/tls"]
 uspace = ["paging", "axcpu/uspace"]
 
 # Custom or default platforms
 myplat = []
-defplat = ["dep:axplat-x86-pc", "dep:axplat-aarch64-qemu-virt", "dep:axplat-riscv64-qemu-virt", "dep:axplat-loongarch64-qemu-virt", "dep:axplat-arm-qemu-virt"]
+defplat = ["dep:axplat-x86-pc", "dep:axplat-aarch64-qemu-virt", "dep:axplat-riscv64-qemu-virt", "dep:axplat-loongarch64-qemu-virt", "dep:axplat-arm-qemu-virt", "dep:axplat-arm-qemu-stm32"]
 
 default = []
 ipi = ["irq"]
@@ -50,6 +50,7 @@ axplat-aarch64-qemu-virt = { version = "0.4", optional = true }
 
 [target.'cfg(target_arch = "arm")'.dependencies]
 axplat-arm-qemu-virt = { version = "0.4", optional = true }
+axplat-arm-qemu-stm32 = { version = "0.1", optional = true }
 
 [target.'cfg(target_arch = "riscv64")'.dependencies]
 axplat-riscv64-qemu-virt = { version = "0.4", optional = true }

modules/axhal/Cargo.toml

@@ -11,20 +11,31 @@ fn main() {
 
 fn gen_linker_script(arch: &str, platform: &str) -> Result<()> {
     let fname = format!("linker_{platform}.lds");
-    let output_arch = if arch == "x86_64" {
-        "i386:x86-64"
-    } else if arch.contains("riscv") {
-        "riscv" // OUTPUT_ARCH of both riscv32/riscv64 is "riscv"
+    let manifest_dir = std::env::var("CARGO_MANIFEST_DIR").unwrap();
+    let workspace_dir = Path::new(&manifest_dir).join("../..");
+    let platform_ld = workspace_dir
+        .join("configs")
+        .join(format!("linker_{platform}.lds"));
+    println!("cargo:rerun-if-changed=linker.lds.S");
+    println!("cargo:rerun-if-changed={}", platform_ld.display());
+    let ld_content = if platform_ld.exists() {
+        std::fs::read_to_string(platform_ld)?
     } else {
-        arch
+        let output_arch = if arch == "x86_64" {
+            "i386:x86-64"
+        } else if arch.contains("riscv") {
+            "riscv" // OUTPUT_ARCH of both riscv32/riscv64 is "riscv"
+        } else {
+            arch
+        };
+        let ld_content = std::fs::read_to_string("linker.lds.S")?;
+        let ld_content = ld_content.replace("%ARCH%", output_arch);
+        let ld_content = ld_content.replace(
+            "%KERNEL_BASE%",
+            &format!("{:#x}", axconfig::plat::KERNEL_BASE_VADDR),
+        );
+        ld_content.replace("%CPU_NUM%", &format!("{}", axconfig::plat::MAX_CPU_NUM))
     };
-    let ld_content = std::fs::read_to_string("linker.lds.S")?;
-    let ld_content = ld_content.replace("%ARCH%", output_arch);
-    let ld_content = ld_content.replace(
-        "%KERNEL_BASE%",
-        &format!("{:#x}", axconfig::plat::KERNEL_BASE_VADDR),
-    );
-    let ld_content = ld_content.replace("%CPU_NUM%", &format!("{}", axconfig::plat::MAX_CPU_NUM));
 
     // target/<target_triple>/<mode>/build/axhal-xxxx/out
     let out_dir = std::env::var("OUT_DIR").unwrap();

modules/axhal/build.rs

@@ -119,7 +119,14 @@ use core::sync::atomic::{AtomicUsize, Ordering};
 /// This function should be called as early as possible, as other initializations
 /// may acess the CPU-local data.
 pub fn init_percpu(cpu_id: usize) {
-    self::percpu::init_primary(cpu_id);
+    #[cfg(target_feature = "mclass")]
+    {
+        let _ = cpu_id;
+    }
+    #[cfg(not(target_feature = "mclass"))]
+    {
+        self::percpu::init_primary(cpu_id);
+    }
 }
 
 /// Initializes CPU-local data structures for secondary cores.

modules/axhal/src/lib.rs

@@ -12,6 +12,9 @@ pub use axplat::mem::{
 };
 pub use memory_addr::{PAGE_SIZE_4K, PhysAddr, PhysAddrRange, VirtAddr, VirtAddrRange, pa, va};
 
+#[cfg(target_feature = "mclass")]
+const MAX_REGIONS: usize = 16;
+#[cfg(not(target_feature = "mclass"))]
 const MAX_REGIONS: usize = 128;
 
 static ALL_MEM_REGIONS: LazyInit<Vec<PhysMemRegion, MAX_REGIONS>> = LazyInit::new();
@@ -29,6 +32,12 @@ pub fn memory_regions() -> impl Iterator<Item = PhysMemRegion> {
 ///
 /// This function is unsafe because it writes `.bss` section directly.
 pub unsafe fn clear_bss() {
+    #[cfg(target_feature = "mclass")]
+    {
+        // Cortex-M platforms clear BSS in their reset handler, before Rust
+        // creates stack frames that may overlap the BSS area in tiny SRAM.
+    }
+    #[cfg(not(target_feature = "mclass"))]
     unsafe {
         core::slice::from_raw_parts_mut(_sbss as usize as *mut u8, _ebss as usize - _sbss as usize)
             .fill(0);
@@ -85,8 +94,16 @@ pub fn init() {
     }
 
     // Combine kernel image range and reserved ranges
-    let kernel_start = virt_to_phys(va!(_skernel as usize)).as_usize();
-    let kernel_size = _ekernel as usize - _skernel as usize;
+    #[cfg(target_feature = "mclass")]
+    let (kernel_start, kernel_size) = (
+        virt_to_phys(va!(_sdata as usize)).as_usize(),
+        _ekernel as usize - _sdata as usize,
+    );
+    #[cfg(not(target_feature = "mclass"))]
+    let (kernel_start, kernel_size) = (
+        virt_to_phys(va!(_skernel as usize)).as_usize(),
+        _ekernel as usize - _skernel as usize,
+    );
     let mut reserved_ranges = reserved_phys_ram_ranges()
         .iter()
         .cloned()