library/util_axis_fifo_asym: guideline review

Fixes the source code to follow the guidelines.
Cosmetic changes only.

Signed-off-by: Carlos Souza <carlos.souza@analog.com>

Author: caosjr

library/util_axis_fifo_asym/util_axis_fifo_asym.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2021-2026 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -84,7 +84,7 @@ module util_axis_fifo_asym #(
 
   localparam MEM_WORD = (TKEEP_EN & TLAST_EN) ? (A_WIDTH+A_WIDTH/8+1) :
                         (TKEEP_EN)            ? (A_WIDTH+A_WIDTH/8)   :
-                        (TLAST_EN)            ? (A_WIDTH+1)              :
+                        (TLAST_EN)            ? (A_WIDTH+1)           :
                                                 (A_WIDTH);
 
   wire [MEM_WORD-1:0] slice_s_data [RATIO-1:0];