Make pins_v2.zig adaptable to multiple chips

Previously pins_v2 was only available on the F303 and L47x, and only
implemented for 7 GPIO ports on the later.

This makes the pins api available to any number of pins (soft limited to
11 due to comptime LUT size). Importer can provide the available number
of ports.

This also makes the api available for stm32f429

Author: JAicewizard

port/stmicro/stm32/src/hals/STM32F303/pins.zig

@@ -1,2 +1,4 @@
-const PinCommon = @import("../common/pins_v2.zig");
+const PinCommon = @import("../common/pins_v2.zig").get_pins(.{
+    .portcount = 7,
+});
 pub const GlobalConfiguration = PinCommon.GlobalConfiguration;

port/stmicro/stm32/src/hals/STM32F429.zig

@@ -30,6 +30,10 @@ const Digital_IO = microzig.drivers.base.Digital_IO;
 
 const State = Digital_IO.State;
 
+pub const pins = @import("./common/pins_v2.zig").get_pins(.{
+    .portcount = 11,
+});
+
 pub const clock = struct {
     pub const Domain = enum {
         cpu,
@@ -47,56 +51,63 @@ pub const clock_frequencies = .{
     .apb2 = 16_000_000,
 };
 
-pub fn parse_pin(comptime spec: []const u8) type {
-    const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme.";
-
-    if (spec[0] != 'P')
-        @compileError(invalid_format_msg);
-    if (spec[1] < 'A' or spec[1] > 'K')
-        @compileError(invalid_format_msg);
-
-    const pin_number: comptime_int = std.fmt.parseInt(u4, spec[2..], 10) catch @compileError(invalid_format_msg);
-
-    return struct {
-        /// 'A'...'K'
-        const gpio_port_name = spec[1..2];
-        const gpio_port = @field(peripherals, "GPIO" ++ gpio_port_name);
-        const suffix = std.fmt.comptimePrint("{d}", .{pin_number});
-    };
-}
+// TODO: There should be a common rcc with stuff like this, just like pins_v2.zig
+pub const rcc = struct {
+    const util = @import("common/util.zig");
+    const _rcc = microzig.chip.peripherals.RCC;
 
-fn set_reg_field(reg: anytype, comptime field_name: anytype, value: anytype) void {
-    var temp = reg.read();
-    @field(temp, field_name) = value;
-    reg.write(temp);
-}
+    // Any peripheral that must be enable in RCC.
+    pub const Peripherals = util.create_peripheral_enum(&.{
+        "GPIO",
+    });
 
-pub const gpio = struct {
-    pub fn set_output(comptime pin: type) void {
-        const AHB1ENR: *volatile @TypeOf(RCC.AHB1ENR) = &RCC.AHB1ENR;
-        const MODER: *volatile @TypeOf(@field(pin.gpio_port, "MODER")) = &@field(pin.gpio_port, "MODER");
-        set_reg_field(AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1);
-        set_reg_field(MODER, "MODER[" ++ pin.suffix ++ "]", .Output);
+    ///configure the power and clock registers before enabling the RTC
+    ///this function also can be called from `rtc.enable()`
+    pub fn enable_rtc(on: bool) void {
+        _rcc.BDCR.modify(.{ .RTCEN = @intFromBool(on) });
     }
 
-    pub fn set_input(comptime pin: type) void {
-        const AHB1ENR: *volatile @TypeOf(RCC.AHB1ENR) = &RCC.AHB1ENR;
-        const MODER: *volatile @TypeOf(@field(pin.gpio_port, "MODER")) = &@field(pin.gpio_port, "MODER");
-        set_reg_field(AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1);
-        set_reg_field(MODER, "MODER[" ++ pin.suffix ++ "]", .Input);
+    pub fn set_clock(comptime peri: Peripherals, state: u1) void {
+        const peri_name = @tagName(peri);
+        const field = peri_name ++ "EN";
+        if (util.match_name(peri_name, &.{"RTC"})) {
+            enable_rtc(state != 0);
+            return;
+        }
+        const rcc_register_name = comptime if (util.match_name(peri_name, &.{
+            "OTGHSULPI",
+            "OTGHS",
+            "ETHMACPTP",
+            "ETHMACRX",
+            "ETHMACTX",
+            "ETHMAC",
+            "DMA2D",
+            "DMA2",
+            "DMA1",
+            "CCMDATARAM",
+            "BKPSRAM",
+            "CRC",
+            "GPIOK",
+            "GPIOJ",
+            "GPIOI",
+            "GPIOH",
+            "GPIOG",
+            "GPIOF",
+            "GPIOE",
+            "GPIOD",
+            "GPIOC",
+            "GPIOB",
+            "GPIOA",
+        })) "AHB1ENR" else "AHB1ENR";
+
+        @field(_rcc, rcc_register_name).modify_one(field, state);
     }
 
-    pub fn read(comptime pin: type) microzig.gpio.State {
-        const idr_reg = pin.gpio_port.IDR;
-        const reg_value = @field(idr_reg.read(), "IDR" ++ pin.suffix); // TODO extract to getRegField()?
-        return @as(microzig.gpio.State, @enumFromInt(reg_value));
+    pub fn enable_clock(comptime peri: Peripherals) void {
+        set_clock(peri, 1);
     }
 
-    pub fn write(comptime pin: type, state: State) void {
-        const BSRR: *volatile @TypeOf(pin.gpio_port.BSRR) = &pin.gpio_port.BSRR;
-        switch (state) {
-            .low => set_reg_field(BSRR, "BR[" ++ pin.suffix ++ "]", 1),
-            .high => set_reg_field(BSRR, "BS[" ++ pin.suffix ++ "]", 1),
-        }
+    pub fn disable_clock(comptime peri: Peripherals) void {
+        set_clock(peri, 0);
     }
 };

port/stmicro/stm32/src/hals/STM32L47X/pins.zig

@@ -1,2 +1,4 @@
-const PinCommon = @import("../common/pins_v2.zig");
+const PinCommon = @import("../common/pins_v2.zig").get_pins(.{
+    .portcount = 8,
+});
 pub const GlobalConfiguration = PinCommon.GlobalConfiguration;