Upstream update available: designs/src/vortex/dev/repo

[claude]

Upstream update available: vortex

Field	Value
Pinned	31e4765d (2025-10-19)
Upstream	f00bb142 (2026-04-24)
Commits behind	84
Days stale	187

Severity: major

Justification: Range introduces a new JTAG DTM / Debug module (with documentation and OpenOCD integration), SST + OpenMPI simulator integration, TF32 in the tensor unit, AXI burst-mode fix for Vivado SmartConnect, and a sim source-tree restructuring with submodules. RTL surface area grows; build system changes; verilator scripts updated.

What changed (highlights)

• Debug / JTAG
  • DebugModule + JTAG DTM for RISC-V; remote bitbang server for OpenOCD
  • 64-bit address handling; variable byte-size memory access in DM
  • Program-completion notification mechanism
  • GDB+OpenOCD debug-mode guide (debug_mode.md)
  • MISA CSR read fix for ELF-in-GDB load
• Simulator integration
  • SST-SIMX redesign / initial integration (PR #298)
  • OpenMPI for Vortex SIMX (PR #282) + MPI regression tests gated behind MPI=1
  • SST script + config + test updates
  • Apptainer CI (#289)
• Tensor / RVV
  • TF32 support in tensor computation + tracing
• AXI / platform
  • Vivado SmartConnect: AXI Burst mode Fixed → Incr (PR #297)
  • U50 platform updates
• Bug fixes
  • io_addr memory-access violation (#267)
  • srai decode fix
  • vx_spawn fix
  • Local mem in simx
  • bss data-race fix
  • memmove direction in RAM::copy + device-match check
  • SST cycle interface return type + exception handling
• Build / CI
  • Verilator download for Ubuntu Focal
  • Toolchain scripts updated for new Verilator + STA tool (the head commit)
  • Drop Ubuntu 22.04 from supported OS list
  • simx source-tree restructuring to support submodules

Recommendation

Defer pending careful integration. The JTAG/DTM addition and tensor-unit TF32 changes will materially shift HighTide asap7 vortex synthesis area. The simx restructuring may break HighTide's designs/src/vortex/dev/setup.sh if it assumed the old tree. Worth integrating eventually for AXI-Incr + bug fixes, but plan re-baselining.

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Last refreshed: 2026-05-11T10:12Z