Upstream update available: designs/src/liteeth/dev/repo

[claude]

Upstream update available: liteeth

Field	Value
Pinned	0eca5086 (2025-05-26)
Upstream	6a6791bf (2026-04-28)
Commits behind	86
Days stale	337

Severity: major

Justification: Range adds two new IP cores (PTP slave, IGMP multicast joiner), a new Altera Agilex3/5 RGMII PHY, configurable MTU/jumbo-frame support, and a CRC engine rewrite. Touches mac/core, mac/sram, PHY layer, and exposes new top-level options — likely affects HighTide's 6 liteeth variants' synthesis area and SDC.

What changed (highlights)

• PTP Slave Core (IEEE 1588v2, Layer 3) — new core/ptp module, with Arty + Acorn Baseboard Mini bench targets and test_ptp.py HDL/servo unit tests (PR #199).
• IGMP Multicast Joiner — new core/igmp integrated into LiteEthIPCore / LiteEthUDPIPCore.
• Agilex3/5 RGMII PHY — new phy/agilex_rgmii.py (PR #202).
• Titanium LVDS 1000BASE-X — large cleanup/refactor across EfinixSerdesDiffTx/Rx, Decoder8b10b{Checker,IdleChecker}, EfinixAligner, EfinixSerdesBuffer; uses LiteX's combinatorial Decoder.
• CRC engine — mac/crc: removed 16-bit support; new checker engine; CRC tests added.
• MAC core dw flexibility — mac/core allows core_dw smaller than phy_dw (PR #177).
• Jumbo frame / configurable MTU, port CDC depth configurable, usrgmii IO delay configuration.
• Titanium/Trion RGMII improvements (multibit IO, ti375 c529 dev board support, ClockDomains numbering).
• RMII uses rx_er if present.
• Misc: LiteEthMACWishboneInterface sets mode, Stream2UDPTX truncation fix, version bumps to 2025.08 and 2025.12, README DeepWiki badge, CI switched to pytest, tests cleaned up.

Recommendation

Update with caution — bench targets and new PHY/IP cores expand surface area but the existing 6 HighTide liteeth variants should still build. Re-baseline area/timing metrics after the bump; the CRC engine rewrite and mac/sram cleanup may shift cell counts. PTP/IGMP are opt-in and won't affect HighTide variants unless explicitly enabled.

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Last refreshed: 2026-05-11T10:12Z