Further AArch64 ISA coverage (#197)

This PR includes all instructions and syscalls added to SimEng in order to begin support for the miniFMM benchmark. Both the GNU and armclang compilers were used to compile this benchmark.

Author: seunghun1ee

src/lib/arch/aarch64/Instruction_address.cc

@@ -277,14 +277,18 @@ span<const MemoryAccessTarget> Instruction::generateAddresses() {
       setMemoryAddresses({{operands[1].get<uint64_t>(), 4}});
       break;
     }
-    case Opcode::AArch64_LDARB: {  // ldar wt, [<xn|sp>]
+    case Opcode::AArch64_LDARB: {  // ldarb wt, [xn]
       setMemoryAddresses({{operands[0].get<uint64_t>(), 1}});
       break;
     }
     case Opcode::AArch64_LDARW: {  // ldar wt, [xn]
       setMemoryAddresses({{operands[0].get<uint64_t>(), 4}});
       break;
     }
+    case Opcode::AArch64_LDARX: {  // ldar xt, [xn]
+      setMemoryAddresses({{operands[0].get<uint64_t>(), 8}});
+      break;
+    }
     case Opcode::AArch64_LDAXRW: {  // ldaxr wd, [xn]
       setMemoryAddresses({{operands[0].get<uint64_t>(), 4}});
       break;
@@ -1073,6 +1077,10 @@ span<const MemoryAccessTarget> Instruction::generateAddresses() {
       setMemoryAddresses({{operands[1].get<uint64_t>(), 4}});
       break;
     }
+    case Opcode::AArch64_STLRX: {  // stlr xt, [xn]
+      setMemoryAddresses({{operands[1].get<uint64_t>(), 8}});
+      break;
+    }
     case Opcode::AArch64_STLXRW: {  // stlxr ws, wt, [xn]
       setMemoryAddresses({{operands[1].get<uint64_t>(), 4}});
       break;

src/lib/arch/aarch64/Instruction_execute.cc

@@ -204,6 +204,16 @@ void Instruction::execute() {
 
   executed_ = true;
   switch (metadata.opcode) {
+    case Opcode::AArch64_ADDv16i8: {  // add vd.16b, vn.16b, vm.16b
+      const uint8_t* n = operands[0].getAsVector<uint8_t>();
+      const uint8_t* m = operands[1].getAsVector<uint8_t>();
+      uint8_t out[16] = {0};
+      for (int i = 0; i < 16; i++) {
+        out[i] = static_cast<uint8_t>(n[i] + m[i]);
+      }
+      results[0] = {out, 256};
+      break;
+    }
     case Opcode::AArch64_ADDv1i64: {  // add dd, dn, dm
       const uint64_t n = operands[0].get<uint64_t>();
       const uint64_t m = operands[1].get<uint64_t>();
@@ -226,6 +236,16 @@ void Instruction::execute() {
       results[0] = {out, 256};
       break;
     }
+    case Opcode::AArch64_ADDv4i16: {  // add vd.4h, vn.4h, vm.4h
+      const uint16_t* n = operands[0].getAsVector<uint16_t>();
+      const uint16_t* m = operands[1].getAsVector<uint16_t>();
+      uint16_t out[8] = {0};
+      for (int i = 0; i < 4; i++) {
+        out[i] = static_cast<uint16_t>(n[i] + m[i]);
+      }
+      results[0] = {out, 256};
+      break;
+    }
     case Opcode::AArch64_ADDv4i32: {  // add vd.4s, vn.4s, vm.4s
       const uint32_t* n = operands[0].getAsVector<uint32_t>();
       const uint32_t* m = operands[1].getAsVector<uint32_t>();
@@ -288,6 +308,26 @@ void Instruction::execute() {
       results[0] = out;
       break;
     }
+    case Opcode::AArch64_ADDv8i16: {  // add vd.8h, vn.8h, vm.8h
+      const uint16_t* n = operands[0].getAsVector<uint16_t>();
+      const uint16_t* m = operands[1].getAsVector<uint16_t>();
+      uint16_t out[8] = {0};
+      for (int i = 0; i < 8; i++) {
+        out[i] = static_cast<uint16_t>(n[i] + m[i]);
+      }
+      results[0] = {out, 256};
+      break;
+    }
+    case Opcode::AArch64_ADDv8i8: {  // add vd.8b, vn.8b, vm.8b
+      const uint8_t* n = operands[0].getAsVector<uint8_t>();
+      const uint8_t* m = operands[1].getAsVector<uint8_t>();
+      uint8_t out[16] = {0};
+      for (int i = 0; i < 8; i++) {
+        out[i] = static_cast<uint8_t>(n[i] + m[i]);
+      }
+      results[0] = {out, 256};
+      break;
+    }
     case Opcode::AArch64_ADCXr: {  // adc xd, xn, xm
       const uint8_t carry = operands[0].get<uint8_t>() & 0b0010;
       const uint64_t n = operands[1].get<uint64_t>();
@@ -3800,14 +3840,18 @@ void Instruction::execute() {
       results[2] = operands[2].get<uint64_t>() + offset;
       break;
     }
-    case Opcode::AArch64_LDARB: {  // LDARB wt, [<xn|sp>]
+    case Opcode::AArch64_LDARB: {  // ldarb wt, [xn]
       results[0] = memoryData[0].zeroExtend(1, 8);
       break;
     }
     case Opcode::AArch64_LDARW: {  // ldar wt, [xn]
       results[0] = memoryData[0].zeroExtend(4, 8);
       break;
     }
+    case Opcode::AArch64_LDARX: {  // ldar xt, [xn]
+      results[0] = memoryData[0];
+      break;
+    }
     case Opcode::AArch64_LDAXRW: {  // ldaxr wd, [xn]
       results[0] = memoryData[0].zeroExtend(4, 8);
       break;
@@ -5374,6 +5418,8 @@ void Instruction::execute() {
     }
     case Opcode::AArch64_STLRB:  // stlrb wt, [xn]
       [[fallthrough]];
+    case Opcode::AArch64_STLRX:  // stlr xt, [xn]
+      [[fallthrough]];
     case Opcode::AArch64_STLRW: {  // stlr wt, [xn]
       memoryData[0] = operands[0];
       break;
@@ -6159,6 +6205,16 @@ void Instruction::execute() {
       results[0] = mulhi(x, y);
       break;
     }
+    case Opcode::AArch64_USHLLv16i8_shift: {  // ushll2 vd.8h, vn.16b, #imm
+      const uint8_t* n = operands[0].getAsVector<uint8_t>();
+      const uint64_t shift = metadata.operands[2].imm;
+      uint16_t out[8] = {0};
+      for (int i = 0; i < 8; i++) {
+        out[i] = n[i + 8] << shift;
+      }
+      results[0] = {out, 256};
+      break;
+    }
     case Opcode::AArch64_USHLLv4i16_shift: {  // ushll vd.4s, vn.4h, #imm
       const uint16_t* n = operands[0].getAsVector<uint16_t>();
       const uint64_t shift = metadata.operands[2].imm;
@@ -6169,6 +6225,26 @@ void Instruction::execute() {
       results[0] = {out, 256};
       break;
     }
+    case Opcode::AArch64_USHLLv8i16_shift: {  // ushll2 vd.4s, vn.8h, #imm
+      const uint16_t* n = operands[0].getAsVector<uint16_t>();
+      const uint64_t shift = metadata.operands[2].imm;
+      uint32_t out[4] = {0};
+      for (int i = 0; i < 4; i++) {
+        out[i] = n[i + 4] << shift;
+      }
+      results[0] = {out, 256};
+      break;
+    }
+    case Opcode::AArch64_USHLLv8i8_shift: {  // ushll vd.8h, vn.8b, #imm
+      const uint8_t* n = operands[0].getAsVector<uint8_t>();
+      const uint64_t shift = metadata.operands[2].imm;
+      uint16_t out[8] = {0};
+      for (int i = 0; i < 8; i++) {
+        out[i] = n[i] << shift;
+      }
+      results[0] = {out, 256};
+      break;
+    }
     case Opcode::AArch64_UUNPKHI_ZZ_D: {  // uunpkhi zd.d, zn.s
       const uint32_t* n = operands[0].getAsVector<uint32_t>();
       const uint64_t VL_bits = 512;

test/regression/aarch64/instructions/load.cc

@@ -265,6 +265,24 @@ TEST_P(InstLoad, ldadd) {
   EXPECT_EQ(getMemoryValue<uint32_t>(process_->getStackPointer() - 928), 128);
 }
 
+TEST_P(InstLoad, ldar) {
+  initialHeapData_.resize(8);
+  uint64_t* heap = reinterpret_cast<uint64_t*>(initialHeapData_.data());
+  heap[0] = 0xDEADBEEF12345678;
+
+  RUN_AARCH64(R"(
+    # Get heap address
+    mov x0, 0
+    mov x8, 214
+    svc #0
+
+    ldar x1, [x0]
+    ldar w2, [x0]
+  )");
+  EXPECT_EQ(getGeneralRegister<uint64_t>(1), 0xDEADBEEF12345678);
+  EXPECT_EQ(getGeneralRegister<uint32_t>(2), 0x12345678);
+}
+
 TEST_P(InstLoad, ldarb) {
   initialHeapData_.resize(8);
   uint32_t* heap = reinterpret_cast<uint32_t*>(initialHeapData_.data());
@@ -276,7 +294,6 @@ TEST_P(InstLoad, ldarb) {
     mov x0, 0
     mov x8, 214
     svc #0
-
     ldarb w1, [x0]
     add x0, x0, #1
     ldarb w2, [x0]
@@ -308,14 +325,11 @@ TEST_P(InstLoad, ldarb) {
     mov w1, #32
     mov w2, #48
     mov w3, #64
-
     str w0, [sp], #32
     str w1, [sp], #32
     str w2, [sp], #32
     str w3, [sp], #32
-
     sub sp, sp, #128
-
     ldarb w4, [sp]
     add sp, sp, #32
     ldarb w5, [sp]
@@ -342,12 +356,10 @@ TEST_P(InstLoad, ldrb) {
     mov x0, 0
     mov x8, 214
     svc #0
-
     ldrb w1, [x0], 1
     ldrb w2, [x0]
     ldrb w3, [x0, 1]!
     ldrb w4, [x0, 2]
-
     mov w5, 1
     ldrb w6, [x0, w5, uxtw]
     mov w5, 3