singlepulse in uvm is not volatile

[pentin-as]

Hello.

When I write in RDL:

field {
  sw = w;
  hw = r;
  singlepulse;
  name = "Reset";
} RESET = 0;

The resulting code is:

this.RESET = uvm_reg_field::type_id::create("RESET");
this.RESET.configure(this, 1, 0, "WO", 0, 'h0, 1, 1, 0);

That is, the volatile bit == 0.

To set volatile to 1, I need to write hw = rw. But that's not true. In fact, hw = r. Furthermore, writing hw = rw will cause unnecessary write signals in the regblock.

I understand that UVM RAL doesn't have the concept of singlepulse. But shouldn't volatile be set to 1?

[antwon87]

I'm not at all a UVM expert, and I'm not sure about volatility, but I think setting the access to W1C makes more sense for singlepulse. It will at least keep the register model consistent with the hardware value in the future. Unless something else in the testbench needs to see a '1' in that field for some reason; I'm not sure if the desired/mirrored values will be updated to 1 and then cleared with W1C...

[pentin-as]

W1C means that the bit is cleared on write:

if (software_write_to_field) begin
  storage_data = 1'b0;
end

single_pulse means that the bit is set on write, but cleared on the next clock cycle:

storage_data = 1'b0;
if (software_write_to_field) begin
  storage_data = 1'b1;
end

It's not possible to specify this behavior in UVM.

But peakrdl currently generates fields with {sw=rw; hw=r; single_pulse} for UVM as non-volatile. Theoretically, this should mean that when software writes a 1, the register should contain a 1. I think this is incorrect.

[amykyta3]

UVM's volatile annotation is actually something that is controlled by the systemrdl-compiler package via the FieldNode.is_volatile helper property.
Moving this issue to that project and will fix there.

[amykyta3]

Fix committed. Will be fixed in the next systemrdl-compiler release