update dcd and cxlmemsim_legacy

Author: vickiegpt

CMakeLists.txt

@@ -44,6 +44,9 @@ endif()
 set(SOURCE_FILES
     src/cxlcontroller.cpp
     src/cxlendpoint.cpp
+    src/dcd_gfam.cpp
+    src/hdm_decoder.cpp
+    src/coherency_engine.cpp
     src/policy.cpp
     src/helper.cpp
 )
@@ -54,6 +57,10 @@ if(CMAKE_SYSTEM_NAME STREQUAL "Linux")
         src/uncore.cpp
         src/perf.cpp
         src/monitor.cpp
+        src/rob.cpp
+        src/lbr.cpp
+        src/pebs.cpp
+        src/perf.cpp
     )
 endif()
 
@@ -63,6 +70,8 @@ add_library(cxlmemsim STATIC ${SOURCE_FILES})
 target_include_directories(cxlmemsim PUBLIC include ${spdlog_INCLUDE_DIR})
 target_link_libraries(cxlmemsim spdlog::spdlog_header_only)
 
+enable_testing()
+
 # Build latency calculator
 add_executable(cxlmemsim_latency src/calculateLatency.cc)
 set_target_properties(cxlmemsim_latency PROPERTIES
@@ -85,7 +94,7 @@ else()
 endif()
 
 # Server library (shared between server executable and tests)
-set(SERVER_LIB_SOURCES src/shared_memory_manager.cc src/shm_communication.cpp src/distributed_server.cpp src/tcp_communication.cpp src/rdma_communication.cpp src/hdm_decoder.cpp src/coherency_engine.cpp)
+set(SERVER_LIB_SOURCES src/shared_memory_manager.cc src/shm_communication.cpp src/distributed_server.cpp src/tcp_communication.cpp src/rdma_communication.cpp)
 add_library(cxlmemsim_server_lib STATIC ${SERVER_LIB_SOURCES})
 target_include_directories(cxlmemsim_server_lib PUBLIC include src ${spdlog_INCLUDE_DIR})
 target_link_libraries(cxlmemsim_server_lib cxlmemsim spdlog::spdlog_header_only ${RT_LIB} ${RDMA_LIBS})
@@ -95,14 +104,46 @@ add_executable(cxlmemsim_server src/main_server.cc)
 target_include_directories(cxlmemsim_server PRIVATE include src ${spdlog_INCLUDE_DIR})
 target_link_libraries(cxlmemsim_server cxlmemsim_server_lib cxlmemsim spdlog::spdlog_header_only ${RT_LIB} ${ATOMIC_LIB})
 
-# Distributed SHM test
+# Build legacy CXLMemSim
+add_executable(cxlmemsim_legacy src/main.cc)
+target_include_directories(cxlmemsim_legacy PRIVATE include src ${spdlog_INCLUDE_DIR})
+target_link_libraries(cxlmemsim_legacy cxlmemsim_server_lib cxlmemsim spdlog::spdlog_header_only ${RT_LIB} ${ATOMIC_LIB})
+
+# Distributed SHM integration test. It opens shared-memory transport state and
+# may start TCP helpers, so build it but keep it out of always-on CTest.
 add_executable(test_distributed_shm tests/test_distributed_shm.cpp)
 target_include_directories(test_distributed_shm PRIVATE include src ${spdlog_INCLUDE_DIR})
 target_link_libraries(test_distributed_shm cxlmemsim_server_lib cxlmemsim spdlog::spdlog_header_only ${RT_LIB} ${ATOMIC_LIB})
 
+# DCD/GFAM unit test (standalone; no server dependencies)
+add_executable(test_dcd_gfam tests/test_dcd_gfam.cpp src/dcd_gfam.cpp)
+target_include_directories(test_dcd_gfam PRIVATE include)
+add_test(NAME test_dcd_gfam COMMAND test_dcd_gfam)
+
+# ROB/O3CPU trace tests
+add_executable(test_rob tests/test_rob.cc src/rob.cpp)
+target_include_directories(test_rob PRIVATE include src ${spdlog_INCLUDE_DIR})
+target_link_libraries(test_rob cxlmemsim spdlog::spdlog_header_only ${RT_LIB} ${ATOMIC_LIB})
+add_test(NAME test_rob COMMAND test_rob)
+
+add_executable(test_mem_stall tests/test_mem_stall.cc src/rob.cpp)
+target_include_directories(test_mem_stall PRIVATE include src ${spdlog_INCLUDE_DIR})
+target_link_libraries(test_mem_stall cxlmemsim spdlog::spdlog_header_only ${RT_LIB} ${ATOMIC_LIB})
+add_test(NAME test_mem_stall COMMAND test_mem_stall)
+
+# Integration-style test clients. They require an external server/DAX setup, so
+# CMake builds them but does not register them as always-on CTest tests.
+add_executable(test_back_invalidation tests/test_back_invalidation.cpp)
+target_include_directories(test_back_invalidation PRIVATE include src)
+target_link_libraries(test_back_invalidation ${RT_LIB} ${ATOMIC_LIB})
+
+add_executable(test_dax_back_invalidation tests/test_dax_back_invalidation.cpp)
+target_include_directories(test_dax_back_invalidation PRIVATE include src)
+target_link_libraries(test_dax_back_invalidation ${RT_LIB} ${ATOMIC_LIB})
+
 # Installation targets
 install(TARGETS cxlmemsim_server
         RUNTIME DESTINATION bin)
 
-install(FILES include/tcp_communication.h include/rdma_communication.h
+install(FILES include/tcp_communication.h include/rdma_communication.h include/dcd_gfam.h
         DESTINATION include/cxlmemsim)

LICENSE

@@ -0,0 +1,29 @@
+BSD 3-Clause License
+
+Copyright (c) 2026 Regents of the University of California, UC Santa Cruz Sluglab.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+   list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+   this list of conditions and the following disclaimer in the documentation
+   and/or other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its
+   contributors may be used to endorse or promote products derived from
+   this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

README.md

@@ -19,6 +19,7 @@ microbench/                            Microbenchmarks
 tests/                                 Server/distributed-mode tests
 qemu_integration/                      Launch scripts and guest-side integration
 qemu_integration/guest_libcuda/        Guest CUDA Driver API shim for CXL Type 2 GPU
+gem5_integration/                      gem5-CXL launch wrapper and O3CPU trace setup
 lib/qemu/                              QEMU tree with CXL Type 2/Type 3 device changes
 lib/qemu/hw/cxl/cxl_type2.c            QEMU CXL Type 2 device model
 lib/qemu/hw/cxl/cxl_hetgpu.c           Host GPU backend bridge
@@ -76,7 +77,8 @@ CXLMemSim adds a server-oriented CXL memory backend. The top-level build always
 - `cxlmemsim`, a static library with the core simulator.
 - `cxlmemsim_server`, the Type 3 memory server.
 - `cxlmemsim_latency`, a latency calculator.
-- `test_distributed_shm`, a distributed shared-memory test.
+- built test binaries for unit and integration checks.
+- CTest targets for DCD/GFAM, ROB, and memory-stall unit behavior.
 
 The server entry point is `src/main_server.cc`. It creates a CXL controller, adds a CXL memory expander endpoint, loads the topology, initializes a shared memory pool, and then serves requests from QEMU or test clients.
 
@@ -88,6 +90,8 @@ Supported request classes include:
 - atomic compare-and-swap,
 - memory fences,
 - Label Storage Area reads and writes.
+- Dynamic Capacity Device add, release, and query operations.
+- GFAM host map, unmap, access-check, and query operations.
 
 The server supports several communication modes:
 
@@ -100,6 +104,8 @@ The server supports several communication modes:
 
 The memory pool is managed by `SharedMemoryManager`. It can use POSIX shared memory or a regular file as a backing store. The shared-memory header records a magic value, format version, total size, data offset, base address, and cache-line count. The default cache-line data area is mapped with `mmap()` and is reused when the backing object already exists.
 
+The server CLI uses local parse-result structs in `src/main_server.cc`, `src/main.cc`, and `src/rob.cc`, so command-line parsing is handled in-tree.
+
 ## Coherency and Distributed Memory
 
 The distributed path is implemented in:
@@ -289,7 +295,7 @@ multiple QEMU guests or server nodes
 
 ## Build
 
-The project uses CMake and C++20. It depends on `cxxopts` and header-only `spdlog`. RDMA support is enabled when `librdmacm` and `libibverbs` are found.
+The project uses CMake and C++20. It depends on header-only `spdlog`; the server and ROB tools use in-tree argument parsing. RDMA support is enabled when `librdmacm` and `libibverbs` are found.
 
 ```bash
 mkdir -p build
@@ -381,6 +387,9 @@ The launcher reads the following runtime variables:
 | `CXL_PGAS_SHM` | `/cxlmemsim_pgas` | POSIX shared-memory object used by QEMU SHM mode. |
 | `CXL_MEMSIM_SERVER_BINARY` | package `bin/cxlmemsim_server` | Server binary started before QEMU. |
 | `CXL_MEMSIM_SERVER_AUTOSTART` | `auto` | Set to `1` to require server startup or `0` to disable it. |
+| `CXL_DCD_ENABLE` | `0` | Enables DCD reporting in integration wrappers. |
+| `CXL_GFAM_ENABLE` | `0` | Enables GFAM reporting in integration wrappers. |
+| `CXL_GFAM_HOST_ID` | `0` | Host ID passed to fabric-aware integrations. |
 
 QEMU's `shm` transport uses the PGAS shared-memory protocol, so the packaged launcher maps `CXL_TRANSPORT_MODE=shm` to the server's `--comm-mode pgas-shm`.
 
@@ -401,6 +410,8 @@ CXL_MEMSIM_PORT=9999 \
 qemu_launch_cxl.sh
 ```
 
+When QEMU connects to `cxlmemsim_server`, the Type 3 device now queries the DCD and GFAM protocol state. If DCD is enabled, QEMU logs the dynamic allocated, total, and free capacity reported by the server. If GFAM is enabled, QEMU logs host, mapping, operation, denied-access, and average-latency counters. Server-side DCD or GFAM denials are returned to QEMU as memory transaction errors instead of being silently treated as successful reads or writes.
+
 Inside the guest, quick checks are:
 
 ```bash
@@ -448,6 +459,24 @@ File-backed memory pool:
   --capacity=1024
 ```
 
+Dynamic Capacity Device and GFAM:
+
+```bash
+./build/cxlmemsim_server \
+  --comm-mode=tcp \
+  --port=9999 \
+  --capacity=10000 \
+  --default_latency=400 \
+  --topology=topology.txt \
+  --enable-dcd \
+  --dcd-granularity-mb=1 \
+  --dcd-initial-capacity=10000 \
+  --enable-gfam \
+  --gfam-hosts=16 \
+  --gfam-fabric-latency=80 \
+  --gfam-bandwidth=64
+```
+
 Useful options:
 
 | Option | Meaning |
@@ -458,8 +487,17 @@ Useful options:
 | `--topology` | Topology file using Newick-style syntax. |
 | `--comm-mode` | `tcp`, `shm`, `pgas-shm`, or `distributed`. |
 | `--backing-file` | Use a regular file instead of POSIX shared memory. |
+| `--enable-dcd` | Enable the Dynamic Capacity Device model. |
+| `--dcd-granularity-mb` | DCD allocation granularity in MB. |
+| `--dcd-initial-capacity` | Initial DCD capacity in MB. Omit it to allocate the full `--capacity`. |
+| `--enable-gfam` | Enable GFAM access control and fabric latency accounting. |
+| `--gfam-hosts` | Number of GFAM host IDs to register. |
+| `--gfam-fabric-latency` | Per-access GFAM fabric latency in ns. |
+| `--gfam-bandwidth` | Aggregate GFAM bandwidth in GB/s. |
 | `SPDLOG_LEVEL` | Runtime log level, for example `debug` or `trace`. |
 
+DCD/GFAM protocol operations are available over TCP and the PGAS shared-memory protocol. Query responses use the 64-byte response data area: DCD query returns total capacity, free capacity, active extents, and failed requests; GFAM query returns mappings, shared mappings, read/write/atomic operations, denied accesses, and average access latency.
+
 ## Distributed Mode
 
 Coordinator node:
@@ -594,6 +632,62 @@ Available tests include:
 - `cxl_pointer_sharing_test`
 - `cxl_bias_benchmark`
 
+## Tests
+
+Configure with CMake and run the self-contained unit tests through CTest:
+
+```bash
+cmake -S . -B build -DCMAKE_BUILD_TYPE=Release
+cmake --build build -j
+ctest --test-dir build --output-on-failure
+```
+
+The top-level CMake file builds every test source in `tests/`:
+
+| Target | Purpose | CTest |
+| --- | --- | --- |
+| `test_dcd_gfam` | Standalone DCD allocation and GFAM access-control checks. | Yes |
+| `test_rob` | Parses O3CPU/LSQ debug lines and feeds derived instructions into the ROB model. | Yes |
+| `test_mem_stall` | Compares O3CPU memory-stall debug intervals against modeled ROB stalls. | Yes |
+| `test_distributed_shm` | Two in-process distributed memory servers over SHM/TCP helper paths. | Built only |
+| `test_back_invalidation` | TCP/PGAS client for external back-invalidation experiments. | Built only |
+| `test_dax_back_invalidation` | DAX plus TCP client for external guest/device experiments. | Built only |
+
+`test_rob` and `test_mem_stall` use gem5-style O3CPU, LSQ, and MemDepUnit debug text. Generate compatible traces with gem5 debug flags such as `O3CPU,LSQ,MemDepUnit`.
+
+## gem5-CXL Integration
+
+`gem5_integration/run.py` is a small launcher for SlugLab's gem5-CXL fork at <https://github.com/SlugLab/gem5-CXL>. It locates a gem5 binary, selects a config script, sets CXLMemSim environment variables, and enables O3CPU trace debug output by default.
+
+Dry-run example:
+
+```bash
+./gem5_integration/run.py \
+  --gem5-root /path/to/gem5-CXL \
+  --config /path/to/gem5-CXL/configs/example/se.py \
+  --cmd /bin/true \
+  --enable-dcd \
+  --enable-gfam \
+  --dry-run
+```
+
+Full-system runs can pass kernel, disk image, workload script, memory size, CXL memory size, and extra gem5 config arguments:
+
+```bash
+./gem5_integration/run.py \
+  --gem5-root /path/to/gem5-CXL \
+  --kernel /path/to/vmlinux \
+  --disk-image /path/to/disk.img \
+  --script boot.rcS \
+  --mem-size 4GB \
+  --cxl-mem-size 16GB \
+  --cxl-host 127.0.0.1 \
+  --cxl-port 9999 \
+  --enable-dcd \
+  --enable-gfam \
+  -- --cpu-type=O3CPU
+```
+
 ## Legacy Application-Level Simulator Invocation
 
 The original CXLMemSim application-level invocation accepts a target executable, sampling interval, CPU set, DRAM latency, bandwidth/latency vectors, capacity vectors, heuristic weights, and topology.